Patents by Inventor Man-Wen TSENG
Man-Wen TSENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250226341Abstract: A bonding structure and a package structure are provided. The bonding structure includes a first pad and a wire bundle structure. The wire bundle structure is protruded from the first pad and tapering away from the first pad. The wire bundle structure includes a first portion and a second portion, the first portion is closer to the first pad than the second portion is, and in a cross-sectional view perspective, a width of a first void in the first portion is less than a width of a second void in the second portion.Type: ApplicationFiled: January 5, 2024Publication date: July 10, 2025Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Ching CHEN, Man-Wen TSENG, Yu-Sheng CHANG, Chia-Cheng HUANG
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Publication number: 20250070075Abstract: A package structure includes a wiring structure, a first electronic device and a reinforcement structure. The first electronic device is disposed over the top surface of the wiring structure, and has a bottom surface facing the top surface of the wiring structure. The first electronic device includes a plurality of first wires. The reinforcement structure is disposed over the top surface of the wiring structure, and includes a plurality of second wires directly contacting the plurality of first wires to reduce a variation of an elevation of the bottom surface of the first electronic device with respect to the top surface of the wiring structure.Type: ApplicationFiled: August 24, 2023Publication date: February 27, 2025Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Yang CHIANG, Man-Wen TSENG, Chien-Ching CHEN
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Patent number: 11088057Abstract: A semiconductor package structure includes a wiring structure, a semiconductor module, a protection layer and a plurality of outer conductive vias. The wiring structure includes at least one dielectric layer and at least one redistribution layer. The semiconductor module is electrically connected to the wiring structure. The semiconductor module has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The protection layer covers the lateral surface of the semiconductor module and a surface of the wiring structure. The outer conductive vias surround the lateral surface of the semiconductor module, electrically connect to the wiring structure, and extend through a dielectric layer of the wiring structure and the protection layer.Type: GrantFiled: May 10, 2019Date of Patent: August 10, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Pin Tsai, Man-Wen Tseng, Yu-Ting Lu
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Patent number: 10879215Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.Type: GrantFiled: March 8, 2019Date of Patent: December 29, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Li-Hao Lyu, Chieh-Ju Tsai, Yu-Kai Lin, Wei-Ming Hsieh, Yu-Pin Tsai, Man-Wen Tseng, Yu-Ting Lu
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Publication number: 20200357730Abstract: A semiconductor package structure includes a wiring structure, a semiconductor module, a protection layer and a plurality of outer conductive vias. The wiring structure includes at least one dielectric layer and at least one redistribution layer. The semiconductor module is electrically connected to the wiring structure. The semiconductor module has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The protection layer covers the lateral surface of the semiconductor module and a surface of the wiring structure. The outer conductive vias surround the lateral surface of the semiconductor module, electrically connect to the wiring structure, and extend through a dielectric layer of the wiring structure and the protection layer.Type: ApplicationFiled: May 10, 2019Publication date: November 12, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yu-Pin TSAI, Man-Wen TSENG, Yu-Ting LU
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Publication number: 20190206843Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.Type: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Li-Hao LYU, Chieh-Ju TSAI, Yu-Kai LIN, Wei-Ming HSIEH, Yu-Pin TSAI, Man-Wen TSENG, Yu-Ting LU
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Patent number: 10269771Abstract: A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive layer, and a second encapsulation layer adjacent to the first encapsulation layer and the adhesive layer. The second encapsulation layer has a first surface and a second surface different from the first surface. A contact angle of the first surface of the second encapsulation layer is different from a contact angle of the second surface of the second encapsulation layer.Type: GrantFiled: August 11, 2017Date of Patent: April 23, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Li-Hao Lyu, Chieh-Ju Tsai, Yu-Kai Lin, Wei-Ming Hsieh, Yu-Pin Tsai, Man-Wen Tseng, Yu-Ting Lu
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Patent number: 10037975Abstract: A semiconductor device package including a first encapsulation layer, a redistribution layer disposed on the first encapsulation layer, a first die disposed on the redistribution layer, a second encapsulation layer covering the first die and the redistribution layer, and an electrical connection terminal electrically connected to the redistribution layer. The first encapsulation layer has a first surface and a second surface different from the first surface. The first encapsulation layer surrounds a portion of the electrical connection terminal and exposes the electrical connection terminal.Type: GrantFiled: August 11, 2017Date of Patent: July 31, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei-Ming Hsieh, Yu-Pin Tsai, Man-Wen Tseng
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Publication number: 20180061813Abstract: A semiconductor device package including a first encapsulation layer, a redistribution layer disposed on the first encapsulation layer, a first die disposed on the redistribution layer, a second encapsulation layer covering the first die and the redistribution layer, and an electrical connection terminal electrically connected to the redistribution layer. The first encapsulation layer has a first surface and a second surface different from the first surface. The first encapsulation layer surrounds a portion of the electrical connection terminal and exposes the electrical connection terminal.Type: ApplicationFiled: August 11, 2017Publication date: March 1, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wei-Ming HSIEH, Yu-Pin TSAI, Man-Wen TSENG, Li-Hao LYU
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Publication number: 20180061727Abstract: A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive layer, and a second encapsulation layer adjacent to the first encapsulation layer and the adhesive layer. The second encapsulation layer has a first surface and a second surface different from the first surface. A contact angle of the first surface of the second encapsulation layer is different from a contact angle of the second surface of the second encapsulation layer.Type: ApplicationFiled: August 11, 2017Publication date: March 1, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Li-Hao LYU, Chieh-Ju TSAI, Yu-Kai LIN, Wei-Ming HSIEH, Yu-Pin TSAI, Man-Wen TSENG, Yu-Ting LU