Patents by Inventor Man Wong

Man Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5718328
    Abstract: A molded plastic current limiting circuit breaker includes an interrupter assembly that includes an over-molded magnet, arc stack, baffle stack, and a chamber liner in which a trip unit is described.
    Type: Grant
    Filed: December 2, 1996
    Date of Patent: February 17, 1998
    Assignee: Square D Company
    Inventors: Timothy Robert Faber, Tak Man Wong
  • Patent number: 5674764
    Abstract: A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 7, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: David K. Liu, Man Wong
  • Patent number: 5612914
    Abstract: A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).
    Type: Grant
    Filed: January 6, 1993
    Date of Patent: March 18, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: David K. Liu, Man Wong
  • Patent number: 5425845
    Abstract: After trench formation on a semiconductor wafer (14) using a hard trench mask containing a phosphosilicate glass top layer and an underlying thermal oxide layer, the phosphosilicate glass layer may be removed without substantially etching the thermal oxide layer. The wafer temperature is increased to at least 40.degree. C. (36) prior to etching with an HF/H.sub.2 O vapor (40-44).
    Type: Grant
    Filed: June 9, 1993
    Date of Patent: June 20, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Man Wong
  • Patent number: 5423944
    Abstract: A method for etching a silicon wafer (20) by using hydrogen fluoride and water vapor combined with ozone is disclosed. The process does not require additional energy excitation or high pressure.
    Type: Grant
    Filed: March 11, 1994
    Date of Patent: June 13, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Man Wong
  • Patent number: 5371402
    Abstract: A method and resulting structure to provide an antifuse wherein the resistance of the programmed fuse and the line resistance and capacitance are materially reduced relative to the prior art and the procedures involved and the resulting structure of the fuse permit the use of materials not available in prior art antifuses. This is accomplished by providing the fuse on vertical sidewalls of the fuse electrode or beneath a sidewall oxide on the fuse electrode. Since the thickness of the electrode can be controlled to an extent not currently achievable by lithographic means, a much smaller area antifuse is provided using sidewall antifuse as opposed to a planar antifuse.
    Type: Grant
    Filed: March 22, 1994
    Date of Patent: December 6, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Man Wong, David K. Liu
  • Patent number: 5250464
    Abstract: A method and resulting structure to provide an antifuse wherein the resistance of the programmed fuse and the line resistance and capacitance are materially reduced relative to the prior art and the procedures involved and the resulting structure of the fuse permit the use of materials not available in prior art antifuses. This is accomplished by providing the fuse on vertical sidewalls of the fuse electrode or beneath a sidewall oxide on the fuse electrode. Since the thickness of the electrode can be controlled to an extent not currently achievable by lithographic means, a much smaller area antifuse is provided using sidewall antifuse as opposed to a planar antifuse.
    Type: Grant
    Filed: March 11, 1992
    Date of Patent: October 5, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Man Wong, David K. Liu
  • Patent number: 5234153
    Abstract: A laser device is bonded to a diamond submount by means of a procedure including (1) codepositing an auxiliary layer, on a layer of barrier metal that has been deposited overlying the submount, followed by (2) depositing a wetting layer on the auxiliary layer, and (3) by depositing a solder layer comprising alternating metallic layers, preferably of gold and tin sufficient to form an overall tin-rich gold-tin eutectic composition. The barrier metal is typically W, Mo, Cr, or Ru. Prior to bonding, a conventional metallization such as Ti-Pt-Au (three layers) is deposited on the laser device's bottom ohmic contact, typically comprising Ge. Then, during bonding, the solder layer is brought into physical contact with the laser device's metallization under enough heat and pressure, followed by cooling, to form a permanent joint between them. The thickness of the solder layer is advantageously less than approximately 5 .mu.m. The wetting layer is preferably the intermetallic compound Ni.sub.3 Sn.sub.
    Type: Grant
    Filed: August 28, 1992
    Date of Patent: August 10, 1993
    Assignee: AT&T Bell Laboratories
    Inventors: Donlad D. Bacon, Avishay Katz, Chien-Hsun Lee, King L. Tai, Yiu-Man Wong
  • Patent number: 5202576
    Abstract: A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).
    Type: Grant
    Filed: June 25, 1991
    Date of Patent: April 13, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: David K. Liu, Man Wong
  • Patent number: 5197654
    Abstract: A device such as a laser is bonded to a submount such as diamond by a process in which the submount is successively coated with an adhesion layer such as titanium, a barrier layer such as nickel, and a gold-tin solder-metallization composite layer formed by sequential deposition on the barrier layer a number (preferably greater than seven) of multiple alternating layers of gold and tin, the last layer being gold having a thickness that is equal to approximately one-half or less than the thickness of the (next-to-last) tin layer that it contacts immediately beneath it. The bonding is performed under applied heat that is sufficient to melt the solder-metallization composite layer. Prior to the bonding, (in addition to the submount) the device advantageously is coated with gold and optionally with a similar gold-tin solder-metallization composite layer, at least at locations where it comes in contact with the gold-tin solder-metallization composite layer.
    Type: Grant
    Filed: November 15, 1991
    Date of Patent: March 30, 1993
    Inventors: Avishay Katz, Chien-Hsun Lee, King L. Tai, Yiu-Man Wong
  • Patent number: 5194948
    Abstract: Alignment of each of a plurality of depending first conductive members (16), in an array of orthogonal rows and columns on an article (12), with a corresponding second conductive member (18) arranged in a like array on a substrate (14), is accomplished by positioning the article in spaced relationship from the substrate. The arrays of first and second conductive members (16,18) are first angularly aligned by rotating the article (12) so that the offset between a first column of first and second conductive members on the article and substrate, respectively, as seen by a television camera (32) at a first end of the article and substrate is the same as the offset between a second column of first and second members on the article and substrate, respectively, at the other end thereof as seen by a second camera (30).
    Type: Grant
    Filed: June 1, 1992
    Date of Patent: March 16, 1993
    Assignee: AT&T Bell Laboratories
    Inventors: Leroy D. L'Esperance, III, Hung N. Nguyen, Yiu-Man Wong
  • Patent number: 5170372
    Abstract: A memory device having an array of memory cells each including a trench capacitor and a pass transistor. The transistor has its source connected to the storage capacitor, its drain connected to a bit line, and its gate connected to a word line. The bit line is formed over a field oxide layer formed on the semiconductor substrate so there is minimal contact between the bit line and the semiconductor substrate. The storage dielectric in the trench is recessed from the surface of the semiconductor substrate.
    Type: Grant
    Filed: April 15, 1992
    Date of Patent: December 8, 1992
    Assignee: Texas Instruments Incorporated
    Inventor: Man Wong
  • Patent number: 5152055
    Abstract: Alignment of each of a plurality of depending first conductive members (16), in an array of orthogonal rows and columns on an article (12), with a corresponding second conductive member (18) arranged in a like array on a substrate (14), is accomplished by positioning the article in spaced relationship from the substrate. The arrays of first and second conductive members (16,18) are first angularly aligned by rotating the article (12) so that the offset between a first column of first and second conductive members on the article and substrate, respectively, as seen by a television camera (32) at a first end of the article and substrate is the same as the offset between a second column of first and second members on the article and substrate, respectively, at the other end thereof as seen by a second camera (30).
    Type: Grant
    Filed: April 26, 1991
    Date of Patent: October 6, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: Leroy D. L'Esperance, III, Hung N. Nguyen, Yiu-Man Wong
  • Patent number: 4069205
    Abstract: A tri(phenylene disulfide) polymer composed of para- or meta-tri(phenylene disulfide) units and units selected from the group consisting of diphenyl ether, bis(phenoxybenzenesulfonyl)benzene and bis(phenoxybenzenesulfonyl)diphenyl ether, is linked together with bivalent radicals selected from the group consisting of isophthaloyl and terephthaloyl radicals. In another embodiment, the tri(phenylene disulfide) can be substituted with biphenylene-2,2'-disulfide.
    Type: Grant
    Filed: September 9, 1976
    Date of Patent: January 17, 1978
    Assignee: University Patents, Inc.
    Inventors: Carl S. Marvel, Daniel Ting-Man Wong
  • Patent number: D401634
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: November 24, 1998
    Assignee: Edu-Science (H.K.) Limited
    Inventor: Chi-Man Wong
  • Patent number: D401977
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: December 1, 1998
    Assignee: Edu-Science (H.K.) Limited
    Inventor: Chi-Man Wong