Abstract: An image decoding unit comprises a decoding unit, a data memory unit, a reconstruction unit, and a frame memory. The decoding unit includes an entropy decoder, a motion compensator, an inverse quantizer, and an inverse DCT unit. The data memory unit includes a data memory A and a data memory B. In the middle of the data transfer from the data memory unit to the frame memory, the reconstruction unit that inputs intermediate data of decoding and outputs reconstructed image data is provided; thereby, the processing of generating the reconstructed image data and the processing of storing the reconstructed image data into the frame memory can be performed in parallel. By the structure, a high-speed processing of image reconstruction can be performed.

Abstract: A total specification is divided into a hardware specification and a software specification. With respect to the hardware specification, a first hardware description is described. With respect to the software specification, an object program is generated, which is converted into a second hardware description. The first and second hardware descriptions are logically synthesized into a net list, which includes a part that fulfills the software specification. Since the object program is converted into the second hardware description, which is logically synthesized, the redundancy of the program can be removed and cost for manufacturing hardware can be reduced.

Abstract: It is decided whether a first source data from the memory 101 is a data which is to be subjected to arithmetic or not by a state flag detection means 150, the result of the decision is retained as a state flag, and it is decided by a condition decision means 109 whether or not the state flag satisfies a condition for performing the arithmetic. A control means 110 controls whether an ALU 100 should perform the arithmetic or not on the basis of the condition satisfaction/dissatisfaction information.

Abstract: An inverse prediction unit inputs decoding information, which is variable-length-decoded data, and target macro block information, which indicates a target macro block. The inverse prediction unit comprises: a brightness/chroma reference value-storing unit; a reference value-initializing unit; an inverse prediction calculation unit; a brightness/chroma prediction value-storing unit; and a following reference value-updating unit. When the target macro block is processed, the reference value-initializing unit determines reference blocks to be initialized according to a predetermined criterion relating to five patterns. The following reference value-updating unit calculates data of the reference blocks that are used in the following inverse prediction processes. It is insufficient that data of the reference blocks are stored until inverse prediction for a target macro block on the next line. A hardware cost for implementing an inverse prediction apparatus can be reduced.

Abstract: A system which allows signal transmission between circuit blocks is constructed promptly by automatically generating an I/F circuit in response to the adjustment of a timing relationship and to a modification in a waveform on a GUI and automatically inserting the I/F circuit between the circuit blocks or adding the I/F circuit to any of the circuit block. A circuit for outputting an operation enable for a receiving side is generated automatically between a plurality of blocks operating with different frequencies, whereby the use of the circuit blocks is expanded in spite of the different frequencies. Further, the design of a large-scale system is performed efficiently by automatically generating a desired waveform by a simple editing operation, generating a desired signal waveform by forming a combinational circuit of signals in the circuit block, and automatically generating a logic synthesis script.

Abstract: An image decoding unit comprises a decoding unit, a data memory unit, a reconstruction unit, and a frame memory. The decoding unit includes an entropy decoder, a motion compensator, an inverse quantizer, and an inverse DCT unit. The data memory unit includes a data memory A and a data memory B. In the middle of the data transfer from the data memory unit to the frame memory, the reconstruction unit that inputs intermediate data of decoding and outputs reconstructed image data is provided; thereby, the processing of generating the reconstructed image data and the processing of storing the reconstructed image data into the frame memory can be performed in parallel. By the structure, a high-speed processing of image reconstruction can be performed.

Abstract: A system which allows signal transmission between circuit blocks is constructed promptly by automatically generating an I/F circuit in response to the adjustment of a timing relationship and to a modification in a waveform on a GUI and automatically inserting the I/F circuit between the circuit blocks or adding the I/F circuit to any of the circuit block. A circuit for outputting an operation enable for a receiving side is generated automatically between a plurality of blocks operating with different frequencies, whereby the use of the circuit blocks is expanded in spite of the different frequencies. Further, the design of a large-scale system is performed efficiently by automatically generating a desired waveform by a simple editing operation, generating a desired signal waveform by forming a combinational circuit of signals in the circuit block, and automatically generating a logic synthesis script.

Abstract: An image processing apparatus according to the present invention comprises a general arithmetic circuit 101 comprising a program control circuit 103, a first address generator 104, a first data memory 105, a first pipeline operation circuit 106, a second address generator 113, a second data memory 114 and a second pipeline operation circuit 112, and a dedicated arithmetic circuit 102 comprising a control circuit 115, a first dedicated pipeline operation circuit 107, a second dedicated pipeline operation circuit 108, . . . , an N-th dedicated pipeline operation circuit 110, as shown in FIG. 1. The arithmetic unit having the above-described structure, for example, can realize an arithmetic unit which can be applied to various applications. Further, considering the age of IP (Intellectual Property) which will come in the future, the arithmetic unit can exhibit the flexibility toward the applications.

Abstract: A high-function address generating apparatus is realized which generates a memory address that can access a multidimensional area without running over a memory area specified by a user. Continuous addressing domain which is determined by a top address and a final address is set by an addressing domain setting means 101, an address is generated by a two-dimensional address generating means 106, the address in a two-dimensional area is compared with the final address and the top address by a first and a second comparing means 108 and 109, respectively, whether it runs over the addressing domain or not is judged by an address correction means 112, and an address running over is corrected so as to not run over.

Abstract: A system which allows signal transmission between circuit locks is constructed promptly by automatically generating an I/F circuit in response to the adjustment of a timing relationship and to a modification in a waveform on a GUI and automatically inserting the I/F circuit between the circuit blocks or adding the I/F circuit to any of the circuit block. A circuit for outputting an operation enable for a receiving side is generated automatically between a plurality of blocks operating with different frequencies, whereby the use of the circuit blocks is expanded in spite of the different frequencies. Further, the design of a large-scale system is performed efficiently by automatically generating a desired waveform by a simple editing operation, generating a desired signal waveform by forming a combinational circuit of signals in the circuit block, and automatically generating a logic synthesis script.

Abstract: A system which allows signal transmission between circuit blocks is constructed promptly by automatically generating an I/F circuit in response to the adjustment of a timing relationship and to a modification in a waveform on a GUI and automatically inserting the I/F circuit between the circuit blocks or adding the I/F circuit to any of the circuit block. A circuit for outputting an operation enable for a receiving side is generated automatically between a plurality of blocks operating with different frequencies, whereby the use of the circuit blocks is expanded in spite of the different frequencies. Further, the design of a large-scale system is performed efficiently by automatically generating a desired waveform by a simple editing operation, generating a desired signal waveform by forming a combinational circuit of signals in the circuit block, and automatically generating a logic synthesis script.

Abstract: A system which allows signal transmission between circuit blocks is constructed promptly by automatically generating an I/F circuit in response to the adjustment of a timing relationship and to a modification in a waveform on a GUI and automatically inserting the I/F circuit between the circuit blocks or adding the I/F circuit to any of the circuit block. A circuit for outputting an operation enable for a receiving side is generated automatically between a plurality of blocks operating with different frequencies, whereby the use of the circuit blocks is expanded in spite of the different frequencies. Further, the design of a large-scale system is performed efficiently by automatically generating a desired waveform by a simple editing operation, generating a desired signal waveform by forming a combinational circuit of signals in the circuit block, and automatically generating a logic synthesis script.

Abstract: For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.

Abstract: For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.

Abstract: For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.