Abstract: An output circuit protected by an abnormal voltage supplied at an output terminal is disclosed. The output circuit comprises a first switching circuit includes first and second transistors connected in series for providing an output terminal with a first potential therethrough in response to a first logic state of a logic signal, a second switching circuit for providing the output terminal with a second potential in response to a second logic state of the logic signal, and means for making the first and second transistors non-conducting when the first switching circuit is disenabled.

Abstract: A semiconductor memory device in which the selected word line is energized only during a limited period of time is disclosed. The memory device is equipped with a clock generator which generates a one-shot pulse signal in response to a change in address signal or to an application of a write-enable signal, and the selected word line is energized by the one-shot clock signal. The clock generator further generates a one-shot clock signal in response to a change in an input data signal in a data-write operation. The input data is thereby sorted into the accessed memory cell, even when the data to be stored is supplied a relatively long time after the write-enable signal is applied.

Abstract: A static semiconductor memory device includes a memory cell matrix having word and digit lines connected to memory cells, an X address decoder connected to the word lines, a gate circuit connected to the digit lines, a Y address decoder connected to a gate of the gate circuit, a sense amplifier connected to an output of the gate circuit, a latching circuit connected to an output of the sense amplifier, and an internal control circuit for supplying control signals to the above components. The internal control circuit controls so as to activate the X address decoder and the sense amplifier, precharge the latching circuit, supply a select signal representing an updated address to the selected word and digit lines, cause the latching circuit to latch a signal appearing across the digit line, and deactivate the X address decoder and the sense amplifier.

Abstract: A driving circuit which can operates stably without being affected by noise or the like is disclosed.