Patents by Inventor Manabu Deura

Manabu Deura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060225012
    Abstract: By providing plural layers in which circuit components of an integrated circuit using plural voltages are arranged in accordance with used voltages, separately arranging the circuit component to which a high voltage is applied in a specific layer among the plural layers, recognizing the used voltage for each layer, and performing a layout verification by applying a condition in accordance with the used voltage, it is possible to recognize the circuit component, to which a high voltage is applied, on the layout, and to perform the layout verification using a layout rule in accordance with the used voltage using only the layers used in an actual process without newly generating a dummy layer etc.
    Type: Application
    Filed: June 27, 2005
    Publication date: October 5, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Manabu Deura
  • Patent number: 6892372
    Abstract: A wiring layout method of an integrated circuit is disclosed. Checking of wiring area ratio is performed after an automatic wiring process. For a wiring other than a grid-shaped wiring, the line width W is classified into three steps of line-width range, and a minimum space width Smin between lines in each step of line-width range is defined in advance to satisfy a condition that Wmax/(Wmax+Smin)?Pmax for a maximum line width Wmax in each step of line-width range. For grid-shaped wirings, a line width W is classified into two steps of line-width range. Further, in its upper step of line-width range, an allowable minimum area Amin (Amin?Amin0) of a metal-removed area A is defined in advance to satisfy a condition that the wiring area ratio P is less than the allowable maximum value Pmax for a maximum line width Wmax. On the other hand, in its lower step of line-width range, made is a definition that the wiring area ratio P is same as the allowable maximum value Pmax for a maximum line width Wmax.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: May 10, 2005
    Assignee: Fujitsu Limited
    Inventor: Manabu Deura
  • Publication number: 20030028853
    Abstract: A wiring layout method of an integrated circuit is disclosed. Checking of wiring area ratio is performed after an automatic wiring process. For a wiring other than a grid-shaped wiring, the line width W is classified into three steps of line-width range, and a minimum space width Smin between lines in each step of line-width range is defined in advance to satisfy a condition that Wmax/(Wmax+Smin)≦Pmax for a maximum line width Wmax in each step of line-width range. For grid-shaped wirings, a line width W is classified into two steps of line-width range. Further, in its upper step of line-width range, an allowable minimum area Amin (Amin≦Amin0) of a metal-removed area A is defined in advance to satisfy a condition that the wiring area ratio P is less than the allowable maximum value Pmax for a maximum line width Wmax. On the other hand, in its lower step of line-width range, made is a definition that the wiring area ratio P is same as the allowable maximum value Pmax for a maximum line width Wmax.
    Type: Application
    Filed: May 6, 2002
    Publication date: February 6, 2003
    Applicant: Fujitsu Limited
    Inventor: Manabu Deura