Patents by Inventor Manabu Fujimura
Manabu Fujimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11683010Abstract: An oscillation circuit includes first and second constant current circuits, first and second switch circuits, first and second MOS transistors, and an output port. The first constant current circuit is connected to one port of a capacitor. The first MOS transistor has a gate and a drain connected to the second constant current circuit and a source connected to another port of the capacitor. The second MOS transistor has a gate connected to the gate of the first MOS transistor, and a drain connected to the one port of the capacitor. The second switch circuit is connected between a source of the second MOS transistor and a second power supply terminal. The output port outputs a signal based on a voltage of the one port. Turn-on and turn-off of the first and second switch circuits are controlled by the signal of the output port and an inverted signal.Type: GrantFiled: July 22, 2022Date of Patent: June 20, 2023Assignee: ABLIC Inc.Inventor: Manabu Fujimura
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Publication number: 20230031567Abstract: An oscillation circuit includes first and second constant current circuits, first and second switch circuits, first and second MOS transistors, and an output port. The first constant current circuit is connected to one port of a capacitor. The first MOS transistor has a gate and a drain connected to the second constant current circuit and a source connected to another port of the capacitor. The second MOS transistor has a gate connected to the gate of the first MOS transistor, and a drain connected to the one port of the capacitor. The second switch circuit is connected between a source of the second MOS transistor and a second power supply terminal. The output port outputs a signal based on a voltage of the one port. Turn-on and turn-off of the first and second switch circuits are controlled by the signal of the output port and an inverted signal.Type: ApplicationFiled: July 22, 2022Publication date: February 2, 2023Applicant: ABLIC Inc.Inventor: Manabu FUJIMURA
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Patent number: 10505500Abstract: Provided is a differential amplification device reduced in DC offset voltage. The amplification device amplifies an input signal, and includes a chopper switch circuit which switches the polarity of the input signal between a normal phase and a reverse phase and outputs the input signal, a V-I conversion circuit which is connected to the chopper switch circuit, a capacitance circuit which is connected to the V-I conversion circuit to store electric charges supplied from the V-I conversion circuit, and an amplification circuit which is connected to the V-I conversion circuit to switch the polarity of an input signal between the normal phase and the reverse phase and amplify the input signal.Type: GrantFiled: March 29, 2018Date of Patent: December 10, 2019Assignee: ABLIC INC.Inventors: Masakazu Sugiura, Toshiyuki Tsuzaki, Yuji Shiine, Manabu Fujimura
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Patent number: 10177655Abstract: Provided is a voltage regulator capable of stably suppressing overshoot. The voltage regulator includes a non-regulated state detection circuit for detecting a non-regulated state, and an overshoot suppression circuit. The overshoot suppression circuit is configured to operate when the non-regulated state detection circuit detects the non-regulated state.Type: GrantFiled: December 15, 2015Date of Patent: January 8, 2019Assignee: ABLIC INC.Inventors: Toshiyuki Tsuzaki, Tadashi Kurozo, Manabu Fujimura
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Patent number: 10148238Abstract: Provided are an amplifier circuit capable of reducing DC offset voltage without an increase in chip area and degradation in frequency characteristics, and a multipath nested miller amplifier circuit. The amplifier circuit includes a chopper switching circuit, a sampling circuit configured to sample an output signal from the chopper switching circuit, and a holding circuit configured to hold a signal output from the sampling circuit.Type: GrantFiled: May 30, 2017Date of Patent: December 4, 2018Assignee: ABLIC INC.Inventors: Masakazu Sugiura, Toshiyuki Tsuzaki, Yuji Shiine, Manabu Fujimura
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Publication number: 20180287567Abstract: Provided is a differential amplification device reduced in DC offset voltage. The amplification device amplifies an input signal, and includes a chopper switch circuit which switches the polarity of the input signal between a normal phase and a reverse phase and outputs the input signal, a V-I conversion circuit which is connected to the chopper switch circuit, a capacitance circuit which is connected to the V-I conversion circuit to store electric charges supplied from the V-I conversion circuit, and an amplification circuit which is connected to the V-I conversion circuit to switch the polarity of an input signal between the normal phase and the reverse phase and amplify the input signal.Type: ApplicationFiled: March 29, 2018Publication date: October 4, 2018Inventors: Masakazu SUGIURA, Toshiyuki TSUZAKI, Yuji SHIINE, Manabu FUJIMURA
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Publication number: 20170353166Abstract: Provided are an amplifier circuit capable of reducing DC offset voltage without an increase in chip area and degradation in frequency characteristics, and a multipath nested miller amplifier circuit. The amplifier circuit includes a chopper switching circuit, a sampling circuit configured to sample an output signal from the chopper switching circuit, and a holding circuit configured to hold a signal output from the sampling circuit.Type: ApplicationFiled: May 30, 2017Publication date: December 7, 2017Inventors: Masakazu SUGIURA, Toshiyuki TSUZAKI, Yuji SHIINE, Manabu FUJIMURA
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Patent number: 9618951Abstract: Provided is a voltage regulator capable of keeping the accuracy of an output voltage thereof even at high temperature. The voltage regulator includes: a reference voltage circuit configured to output a reference voltage; an output transistor configured to output an output voltage; a voltage divider circuit configured to divide the output voltage to output a divided voltage; an error amplifier circuit configured to amplify a difference between the reference voltage and the divided voltage, and output the amplified difference to control a gate of the output transistor; a switching circuit configured to switch the divided voltage of the voltage divider circuit; and a temperature detection circuit configured to output a signal in accordance with temperature to control the switching circuit.Type: GrantFiled: October 13, 2014Date of Patent: April 11, 2017Assignee: SII SEMICONDUCTOR CORPORATIONInventors: Yuji Kobayashi, Manabu Fujimura
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Publication number: 20160105113Abstract: Provided is a voltage regulator capable of stably suppressing overshoot. The voltage regulator includes a non-regulated state detection circuit for detecting a non-regulated state, and an overshoot suppression circuit. The overshoot suppression circuit is configured to operate when the non-regulated state detection circuit detects the non-regulated state.Type: ApplicationFiled: December 15, 2015Publication date: April 14, 2016Inventors: Toshiyuki TSUZAKI, Tadashi KUROZO, Manabu FUJIMURA
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Publication number: 20160099645Abstract: To provide a voltage regulator capable of using as a capacitor of a phase compensation circuit, a capacitor large in capacitance value per unit area and thin in oxidation film thickness. A voltage limitation circuit that limits so that a voltage applied across a capacitor of a phase compensation circuit does not reach a predetermined value or greater is provided in parallel with the capacitor.Type: ApplicationFiled: December 14, 2015Publication date: April 7, 2016Inventors: Manabu FUJIMURA, Minoru SUDO
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Patent number: 9141121Abstract: Provided is a voltage regulator capable of suppressing excessive overshoot at the output terminal when the power supply fluctuates in a non-regulate state. The voltage regulator includes: an error amplification circuit that amplifies a difference between reference voltage and divided voltage, thus controlling a gate of an output transistor; an amplifier that compares the reference voltage and the divided voltage to detect overshoot at the output voltage; a first transistor that lets current that is proportional to current flowing through the output transistor pass therethrough; a current mirror circuit that mirrors current that is proportional to the current flowing through the output transistor; and a first bias circuit connected to the amplifier via the current mirror circuit, the first bias circuit increasing bias current of the amplifier to increase a response speed.Type: GrantFiled: August 30, 2013Date of Patent: September 22, 2015Assignee: SEIKO INSTRUMENTS INC.Inventors: Yotaro Nihei, Manabu Fujimura
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Publication number: 20150102789Abstract: Provided is a voltage regulator capable of keeping the accuracy of an output voltage thereof even at high temperature. The voltage regulator includes: a reference voltage circuit configured to output a reference voltage; an output transistor configured to output an output voltage; a voltage divider circuit configured to divide the output voltage to output a divided voltage; an error amplifier circuit configured to amplify a difference between the reference voltage and the divided voltage, and output the amplified difference to control a gate of the output transistor; a switching circuit configured to switch the divided voltage of the voltage divider circuit; and a temperature detection circuit configured to output a signal in accordance with temperature to control the switching circuit.Type: ApplicationFiled: October 13, 2014Publication date: April 16, 2015Inventors: Yuji KOBAYASHI, Manabu FUJIMURA
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Patent number: 8957659Abstract: Provided is a voltage regulator having improved transient response characteristics even when a load current is switched from a light load to a heavy load. The voltage regulator includes, to a gate of a detection transistor constituting an output current detection circuit: a resistive element for interrupting the gate of the detection transistor from an output terminal of a differential amplifier circuit in an AC manner; and a capacitive element connected to an output terminal of the voltage regulator in an AC manner.Type: GrantFiled: February 27, 2013Date of Patent: February 17, 2015Assignee: Seiko Instruments Inc.Inventors: Manabu Fujimura, Takashi Imura, Yuji Kobayashi
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Publication number: 20140070778Abstract: Provided is a voltage regulator capable of suppressing excessive overshoot at the output terminal when the power supply fluctuates in a non-regulate state. The voltage regulator includes: an error amplification circuit that amplifies a difference between reference voltage and divided voltage, thus controlling a gate of an output transistor; an amplifier that compares the reference voltage and the divided voltage to detect overshoot at the output voltage; a first transistor that lets current that is proportional to current flowing through the output transistor pass therethrough; a current mirror circuit that mirrors current that is proportional to the current flowing through the output transistor; and a first bias circuit connected to the amplifier via the current mirror circuit, the first bias circuit increasing bias current of the amplifier to increase a response speed.Type: ApplicationFiled: August 30, 2013Publication date: March 13, 2014Applicant: Seiko Instruments Inc.Inventors: Yotaro NIHEI, Manabu FUJIMURA
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Publication number: 20130234687Abstract: Provided is a voltage regulator having improved transient response characteristics even when a load current is switched from a light load to a heavy load. The voltage regulator includes, to a gate of a detection transistor constituting an output current detection circuit: a resistive element for interrupting the gate of the detection transistor from an output terminal of a differential amplifier circuit in an AC manner; and a capacitive element connected to an output terminal of the voltage regulator in an AC manner.Type: ApplicationFiled: February 27, 2013Publication date: September 12, 2013Applicant: SEIKO INSTRUMENTS INC.Inventors: Manabu FUJIMURA, Takashi IMURA, Yuji KOBAYASHI
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Patent number: 8502529Abstract: Provided is a magnetic sensor device capable of suppressing a variation in determination for detection or canceling of a magnetic field intensity, which is caused by noise generated from respective constituent elements included in the magnetic sensor device and external noise, to thereby achieve high-precision magnetic reading. The magnetic sensor device includes: a first D-type flip-flop and a second D-type flip-flop each having an input terminal connected to an output terminal of a comparator; an XOR circuit having a first input terminal and a second input terminal which are connected to an output terminal of the first D-type flip-flop and an output terminal of the second D-type flip-flop, respectively; a selector circuit; and a third D-type flip-flop having an input terminal connected to an output terminal of the selector circuit.Type: GrantFiled: November 30, 2010Date of Patent: August 6, 2013Assignee: Seiko Instruments Inc.Inventors: Daisuke Muraoka, Minoru Ariyama, Tomoki Hikichi, Manabu Fujimura
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Patent number: 8476891Abstract: Provided is a constant current circuit capable of low current consumption operation, which is prevented from repeating a start-up state and a zero steady state and entering an oscillating state when power is activated. When power is activated, until a node (A) reaches a start-up state, an excitation current is continued to be supplied to a node (B), to thereby reliably start up the constant current circuit in a short period of time without repeating the start-up state and the zero steady state.Type: GrantFiled: November 30, 2010Date of Patent: July 2, 2013Assignee: Seiko Instruments Inc.Inventors: Tomoki Hikichi, Minoru Ariyama, Daisuke Muraoka, Manabu Fujimura
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Patent number: 8207778Abstract: Provided is a physical quantity sensor capable of improving physical quantity detection precision thereof. The physical quantity sensor includes a bridge resistance type physical quantity detection element for generating a voltage based on a bias current and a physical quantity, a current supply circuit for supplying the bias current to the physical quantity detection element, and a leakage current control circuit for causing leakage currents flowing when switches of the current supply circuit are in an off state to flow into a ground terminal.Type: GrantFiled: December 6, 2010Date of Patent: June 26, 2012Assignee: Seiko Instruments Inc.Inventors: Manabu Fujimura, Minoru Ariyama, Daisuke Muraoka, Tomoki Hikichi
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Patent number: 8193807Abstract: Provided is a magnetic sensor device including: a switching circuit that controls switching of a terminal pair of the magnetoelectric conversion element to which a supply voltage is applied and a terminal pair to which detection voltage of a magnetic intensity is output; a differential amplifier that differentially amplifies the detection voltage; a first capacitor connected to a first output terminal of the differential amplifier; a second switch connected to a second output terminal of the differential amplifier; a comparator that has a first input terminal connected to the first capacitor and a second input terminal connected to the second switch; a first switch connected between the first input terminal and an output terminal of the comparator; and a second capacitor connected to the second input terminal of the comparator; and a detection voltage setting circuit connected to the second capacitor, in which effects of respective offset voltages of the magnetoelectric conversion element, the amplifier, andType: GrantFiled: May 13, 2010Date of Patent: June 5, 2012Assignee: Seiko Instruments Inc.Inventors: Daisuke Muraoka, Minoru Ariyama, Tomoki Hikichi, Manabu Fujimura
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Publication number: 20110241662Abstract: Provided is a magnetic sensor device capable of suppressing a variation in determination for detection or canceling of a magnetic field intensity, which is caused by noise generated from respective constituent elements included in the magnetic sensor device and external noise, to thereby achieve high-precision magnetic reading. The magnetic sensor device includes: a first D-type flip-flop and a second D-type flip-flop each having an input terminal connected to an output terminal of a comparator; an XOR circuit having a first input terminal and a second input terminal which are connected to an output terminal of the first D-type flip-flop and an output terminal of the second D-type flip-flop, respectively; a selector circuit; and a third D-type flip-flop having an input terminal connected to an output terminal of the selector circuit.Type: ApplicationFiled: November 30, 2010Publication date: October 6, 2011Inventors: Daisuke Muraoka, Minoru Ariyama, Tomoki Hikichi, Manabu Fujimura