Abstract: A ring oscillator including: an oscillation circuit including an even number of inverters connected in a ring configuration, the oscillation circuit outputting a clock signal; plural potential fixing circuits respectively connected between pairs of the inverters, each of plural potential fixing circuits being switchable between a connected and a disconnected state in response to a first control signal; and an adjustment circuit that adjusts a drive capability of the inverters based on a second control signal, wherein, during startup, the drive capability is controlled to be a first capability, in which the potential fixing circuits are connected, by the first control signal, and wherein, after a predetermined time has elapsed after the first control signal is output, the drive capability is controlled to be a second capability, higher than the first capability, in which the potential fixing circuits are disconnected, by the second control signal.

Abstract: A semiconductor device includes: a pair of input terminals or receiving a first input signal and a second input signal each of which changes between potentials in a predetermined range via a pair of transmission paths which include a first transmission path and a second transmission path; a first reception circuit which compares in potential the first input signal with the second input signal, and generates a first output signal based on a comparison result therebetween; a second reception circuit which generates a second output signal based on a comparison result of comparing in potential at least one of the first input signal and the second input signal with a reference potential.

Abstract: A ring oscillator including: an oscillation circuit including an even number of inverters connected in a ring configuration, the oscillation circuit outputting a clock signal; plural potential fixing circuits respectively connected between pairs of the inverters, each of plural potential fixing circuits being switchable between a connected and a disconnected state in response to a first control signal; and an adjustment circuit that adjusts a drive capability of the inverters based on a second control signal, wherein, during startup, the drive capability is controlled to be a first capability, in which the potential fixing circuits are connected, by the first control signal, and wherein, after a predetermined time has elapsed after the first control signal is output, the drive capability is controlled to be a second capability, higher than the first capability, in which the potential fixing circuits are disconnected, by the second control signal.

Abstract: A semiconductor device includes: a pair of input terminals or receiving a first input signal and a second input signal each of which changes between potentials in a predetermined range via a pair of transmission paths which include a first transmission path and a second transmission path; a first reception circuit which compares in potential the first input signal with the second input signal, and generates a first output signal based on a comparison result therebetween; a second reception circuit which generates a second output signal based on a comparison result of comparing in potential at least one of the first input signal and the second input signal with a reference potential.

Abstract: A phase locked loop circuit according to the present invention includes a selector that selects an input clock, a 1/m frequency divider that divides a frequency of the input clock, a 1/n frequency divider that divides a frequency of a feedback clock, a phase difference detector, a first voltage controlled oscillator that includes a first voltage holding circuit, a second voltage controlled oscillator that includes a second voltage holding circuit, and a selection circuit that outputs any output of the first and second voltage controlled oscillators as an output clock and outputs any output of the first and second voltage controlled oscillators as a feedback clock. The input clock is switched when the voltage controlled oscillator in a holding mode generates the output clock and the voltage controlled oscillator in a normal mode generates the feedback clock.

Abstract: A phase locked loop circuit according to the present invention includes a selector that selects an input clock, a 1/m frequency divider that divides a frequency of the input clock, a 1/n frequency divider that divides a frequency of a feedback clock, a phase difference detector, a first voltage controlled oscillator that includes a first voltage holding circuit, a second voltage controlled oscillator that includes a second voltage holding circuit, and a selection circuit that outputs any output of the first and second voltage controlled oscillators as an output clock and outputs any output of the first and second voltage controlled oscillators as a feedback clock. The input clock is switched when the voltage controlled oscillator in a holding mode generates the output clock and the voltage controlled oscillator in a normal mode generates the feedback clock.

Abstract: A phase-locked loop circuit includes a phase detector detecting a phase difference between a first clock and a second clock; a voltage controlled oscillator outputting the second clock based on an input voltage that fluctuates corresponding to the phase difference detected by the phase detector; and a selector selecting the first clock from a plurality of clocks based on a clock change signal that is transmitted to the selector while the input voltage is set substantially constant.