Patents by Inventor Manabu Gokan

Manabu Gokan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200359114
    Abstract: A wireless sensor system capable of operating with low power and capable of perming long-distance and high-speed data transmission includes a plurality of sensor nodes acquiring prescribed measurement data and a relay spot receiving measurement data relay-transmitted among the sensor nodes and transmitting the measurement data to a given communication device (for example, a gateway) by a LPWA (Low Power Wide Area) communication. A switching operation between a reception side (Central) and a transmission side (Peripheral) is performed in an asynchronous manner among the sensor nodes performing transmission and reception of the measurement data.
    Type: Application
    Filed: April 1, 2020
    Publication date: November 12, 2020
    Inventors: MANABU GOKAN, JUNYA TANAKA, KEIKO TAKAHASHI
  • Publication number: 20170341188
    Abstract: To provide a solder material capable of performing soldering with high reliability while suppressing materials other than a solder metal to remain inside the solder after the soldering. Coil-shaped carbons are heated by electromagnetic waves by using a solder material in which coil-shaped carbons of 0.5 weight % to 1.5 weight % with respect to a weight of a solder paste are mixed, thereby performing soldering by heating the solder material itself.
    Type: Application
    Filed: April 4, 2017
    Publication date: November 30, 2017
    Inventors: SHINJI ISHITANI, MANABU GOKAN, TATSUO SASAOKA
  • Patent number: 8237057
    Abstract: A wiring board is provided that suppresses spreading of liquid droplets when liquid droplets are discharged using an ink-jet method. The wiring board has a plurality of layers and includes an ink-jet wiring pattern that is formed in a soluble porous membrane member of any single layer and that includes electrically conductive nanoparticles as a principal material, and a transferred wiring pattern that does not include electrically conductive nanoparticles as a principal material. One layer among the plurality of layers is an electrically insulative substrate. Another layer among the plurality of layers is a porous membrane treated member layer including a porous membrane member at one part of a region of the other layer. The ink-jet wiring pattern is formed in the porous membrane treated member layer. The transferred wiring pattern is formed in the substrate.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: August 7, 2012
    Assignee: Panasonic Corporation
    Inventors: Takayuki Hirose, Norihito Tsukahara, Manabu Gokan
  • Patent number: 8093505
    Abstract: Provided is a layered electronic circuit device capable of realizing high-density/high-function mounting, easily inspecting and repairing the respective constituent elements, and improving the electronic connection characteristic. The layered electronic circuit device includes a first circuit substrate (101) and a second circuit substrate (102) which are arranged in parallel such that their substrate surfaces are opposed to each other. The peripheral portion of the first circuit substrate (101) and the peripheral portion of the second circuit substrate (102) are connected to each other by connection members (10a to 10d) having a wiring member (103) and a thermal hardening anisotropic conductive sheet (107), thereby performing electric connection.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: January 10, 2012
    Assignee: Panasonic Corporation
    Inventors: Manabu Gokan, Akihisa Nakahashi, Takayuki Hirose, Yoko Kasai, Kohichi Tanda
  • Patent number: 7875974
    Abstract: To provide a stacked mounting structure in which the number of semiconductor chips that can be stacked is greater than conventionally, as well as a method for fabricating the same, each semiconductor chip has electrodes provided at least at one end in the stacked mounting structure, and a board holding the semiconductor chips at the one end is folded with at least two of the semiconductor chips being stacked so as to at least partially overlap with each other.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: January 25, 2011
    Assignee: Panasonic Corporation
    Inventors: Manabu Gokan, Akihisa Nakahashi, Naoki Suzuki, Haneo Iwamoto, Satoru Yuhaku
  • Patent number: 7808094
    Abstract: A stacked structure of semiconductor chips includes plural stacked semiconductor chips and plural tabular holding members which hold the respective semiconductor chips.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: October 5, 2010
    Assignee: Panasonic Corporation
    Inventors: Manabu Gokan, Akihisa Nakahashi, Koichi Nagai, Naoki Suzuki
  • Publication number: 20100230147
    Abstract: Provided is a layered electronic circuit device capable of realizing high-density/high-function mounting, easily inspecting and repairing the respective constituent elements, and improving the electronic connection characteristic. The layered electronic circuit device includes a first circuit substrate (101) and a second circuit substrate (102) which are arranged in parallel such that their substrate surfaces are opposed to each other. The peripheral portion of the first circuit substrate (101) and the peripheral portion of the second circuit substrate (102) are connected to each other by connection members (10a to 10d) having a wiring member (103) and a thermal hardening anisotropic conductive sheet (107), thereby performing electric connection.
    Type: Application
    Filed: August 10, 2007
    Publication date: September 16, 2010
    Applicant: Panasonic Corporation
    Inventors: Manabu Gokan, Akihisa Nakahashi, Takayuki Hirose, Yoko Kasai, Kohichi Tanda
  • Publication number: 20090314528
    Abstract: A wiring board is provided that suppresses spreading of liquid droplets when liquid droplets are discharged using an ink-jet method. The wiring board has a plurality of layers and includes an ink-jet wiring pattern that is formed in a soluble porous membrane member of any single layer and that includes electrically conductive nanoparticles as a principal material, and a transferred wiring pattern that does not include electrically conductive nanoparticles as a principal material. One layer among the plurality of layers is an electrically insulative substrate. Another layer among the plurality of layers is a porous membrane treated member layer including a porous membrane member at one part of a region of the other layer. The ink-jet wiring pattern is formed in the porous membrane treated member layer. The transferred wiring pattern is formed in the substrate.
    Type: Application
    Filed: June 17, 2009
    Publication date: December 24, 2009
    Applicant: Panasonic Corporation
    Inventors: Takayuki Hirose, Norihito Tsukahara, Manabu Gokan
  • Publication number: 20090166838
    Abstract: To provide a stacked mounting structure in which the number of semiconductor chips that can be stacked is greater than conventionally, as well as a method for fabricating the same, each semiconductor chip has electrodes provided at least at one end in the stacked mounting structure, and a board holding the semiconductor chips at the one end is folded with at least two of the semiconductor chips being stacked so as to at least partially overlap with each other.
    Type: Application
    Filed: December 17, 2008
    Publication date: July 2, 2009
    Inventors: Manabu Gokan, Akihisa Nakahashi, Naoki Suzuki, Haneo Iwamoto, Satoru Yuhaku
  • Publication number: 20090166839
    Abstract: A semiconductor stack device having semiconductor chips stacked therein, wherein pads 4d of an uppermost semiconductor chip 2d are disposed on the side of a base substrate 1, and the pads 4d of the semiconductor chip 2d and electrodes 8d of the base substrate 1 are connected to each other via a flexible substrate 5 having circuit components 7 mounted thereon.
    Type: Application
    Filed: December 23, 2008
    Publication date: July 2, 2009
    Applicant: Panasonic Corporation
    Inventors: Naoki Suzuki, Akihisa Nakahashi, Haneo Iwamoto, Manabu Gokan, Satoru Yuhaku
  • Publication number: 20080185731
    Abstract: A stacked structure of semiconductor chips includes plural stacked semiconductor chips and plural tabular holding members which hold the respective semiconductor chips.
    Type: Application
    Filed: January 30, 2008
    Publication date: August 7, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Manabu Gokan, Akihisa Nakahashi, Koichi Nagai, Naoki Suzuki