Patents by Inventor Manabu Imahashi
Manabu Imahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8188568Abstract: A semiconductor circuit includes: a first diffusion layer formed on a substrate; a second diffusion layer formed in an upper part of the first diffusion layer; a third diffusion layer formed in an upper part of the second diffusion layer; a fourth diffusion layer formed in the upper part of the first diffusion layer; and a fifth diffusion formed below the third diffusion layer. A sum of a shortest distance from the third diffusion layer to the fifth diffusion layer and a shortest distance from the fifth diffusion layer or the lower end of the first diffusion layer to the fourth diffusion layer is smaller than a shortest distance from the third diffusion layer to the fourth diffusion layer. The substrate, the second and the fifth diffusion layer are a first conductivity type and the others are a second conductivity type.Type: GrantFiled: February 7, 2011Date of Patent: May 29, 2012Assignee: Panasonic CorporationInventor: Manabu Imahashi
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Patent number: 8148778Abstract: A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer layer is formed between the first well diffusion layer and the third well diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer, and extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer. The buffer layer has an impurity concentration lower than an impurity concentration in the third well diffusion layer.Type: GrantFiled: March 17, 2011Date of Patent: April 3, 2012Assignee: Panasonic CorporationInventors: Yasushi Kobayashi, Manabu Imahashi
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Publication number: 20110254120Abstract: A semiconductor integrated circuit includes: a substrate of a first conductivity type; a first diffusion layer of a second conductivity type formed on the substrate; a second diffusion layer of the first conductivity type formed in an upper part of the first diffusion layer; a third diffusion layer of the second conductivity type formed in an upper part of the second diffusion layer; a fourth diffusion layer of the second conductivity type formed in the upper part of the first diffusion layer; and a fifth diffusion layer of the first conductivity type formed below the third diffusion layer. A sum of a shortest distance from the third diffusion layer to the fifth diffusion layer and a shortest distance from the fifth diffusion layer or the lower end of the first diffusion layer to the fourth diffusion layer is smaller than a shortest distance from the third diffusion layer to the fourth diffusion layer.Type: ApplicationFiled: February 7, 2011Publication date: October 20, 2011Inventor: Manabu IMAHASHI
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Publication number: 20110163377Abstract: A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer layer is formed between the first well diffusion layer and the third well diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer, and extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer. The buffer layer has an impurity concentration lower than an impurity concentration in the third well diffusion layer.Type: ApplicationFiled: March 17, 2011Publication date: July 7, 2011Applicant: PANASONIC CORPORATIONInventors: Yasushi KOBAYASHI, Manabu Imahashi
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Patent number: 7932558Abstract: A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer layer is formed between the first well diffusion layer and the third well diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer, and extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer. The buffer layer has an impurity concentration lower than an impurity concentration in the third well diffusion layer.Type: GrantFiled: April 15, 2009Date of Patent: April 26, 2011Assignee: Panasonic CorporationInventors: Yasushi Kobayashi, Manabu Imahashi
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Patent number: 7821029Abstract: An electrostatic protection element relating to the present invention comprises a P-type semiconductor and an N-type first impurity layer provided in the semiconductor substrate. The first impurity layer comprises a P-type second impurity layer functioning as a gate. The second impurity layer comprises an N-type third impurity layer functioning as a cathode. Further, the first impurity layer comprises an N-type fourth impurity layer spaced apart from the second impurity layer at a distance. The fourth impurity layer comprises a P-type fifth impurity layer functioning as an anode and an N-type sixth impurity layer. Then, in the electrostatic protection element, an impurity concentration of the fourth impurity layer is higher than that of the first impurity layer, and a bottom of the fourth impurity layer is deeper than that of the second impurity layer.Type: GrantFiled: August 18, 2009Date of Patent: October 26, 2010Assignee: Panasonic CorporationInventor: Manabu Imahashi
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Publication number: 20100044750Abstract: An electrostatic protection element relating to the present invention comprises a P-type semiconductor and an N-type first impurity layer provided in the semiconductor substrate. The first impurity layer comprises a P-type second impurity layer functioning as a gate. The second impurity layer comprises an N-type third impurity layer functioning as a cathode. Further, the first impurity layer comprises an N-type fourth impurity layer spaced apart from the second impurity layer at a distance. The fourth impurity layer comprises a P-type fifth impurity layer functioning as an anode and an N-type sixth impurity layer. Then, in the electrostatic protection element, an impurity concentration of the fourth impurity layer is higher than that of the first impurity layer, and a bottom of the fourth impurity layer is deeper than that of the second impurity layer.Type: ApplicationFiled: August 18, 2009Publication date: February 25, 2010Inventor: Manabu IMAHASHI
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Publication number: 20090267144Abstract: A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer layer is formed between the first well diffusion layer and the third well diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer, and extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer. The buffer layer has an impurity concentration lower than an impurity concentration in the third well diffusion layer.Type: ApplicationFiled: April 15, 2009Publication date: October 29, 2009Inventors: Yasushi KOBAYASHI, Manabu Imahashi
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Publication number: 20070210419Abstract: An electrostatic discharge protection device of a semiconductor integrated circuit, comprising a first diffusion layer that is a diffusion layer of a second conductivity type provided on a semiconductor substrate of a first conductivity type and serves as a collector, a second diffusion layer that is a diffusion layer of the first conductivity type provided in the first diffusion layer and serves as a base, a third diffusion layer that is a diffusion layer of the second conductivity type provided in the second diffusion layer and serves as an emitter, a collector contact region provided in the first diffusion layer, a fourth diffusion layer that is a diffusion layer of the second conductivity type provided in the first diffusion layer in a downward region of the collector contact region in a substrate-thickness direction, wherein the fourth diffusion layer is formed shallower in a depth than that of the first diffusion layer in the substrate-thickness direction, deeper in a depth than that of the second diffuType: ApplicationFiled: March 8, 2007Publication date: September 13, 2007Inventors: Masakatsu Nawate, Manabu Imahashi
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Patent number: 7202531Abstract: A semiconductor device includes an output pad and a surge absorption unit formed above a semiconductor region of a first conductivity type. The surge absorption unit includes: a semiconductor island region of a second conductivity type; a buried layer of the second conductivity type formed between a bottom of the semiconductor island region of the second conductivity type and the semiconductor region of the first conductivity type; a dopant layer of the first conductivity type formed in an upper portion of the semiconductor island region of the second conductivity type and connected to have the same potential as the semiconductor region of the first conductivity type; a dopant layer of the second conductivity type formed in an upper portion of the dopant layer of the first conductivity type and electrically connected to the output pad; and a ring layer of the second conductivity type surrounding the dopant layer of the first conductivity type and reaching the buried layer of the second conductivity type.Type: GrantFiled: March 22, 2005Date of Patent: April 10, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Manabu Imahashi, Hiroyoshi Ogura, Masakatsu Nawate
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Publication number: 20050230761Abstract: A semiconductor device includes an output pad and a surge absorption unit formed above a semiconductor region of a first conductivity type. The surge absorption unit includes: a semiconductor island region of a second conductivity type; a buried layer of the second conductivity type formed between a bottom of the semiconductor island region of the second conductivity type and the semiconductor region of the first conductivity type; a dopant layer of the first conductivity type formed in an upper portion of the semiconductor island region of the second conductivity type and connected to have the same potential as the semiconductor region of the first conductivity type; a dopant layer of the second conductivity type formed in an upper portion of the dopant layer of the first conductivity type and electrically connected to the output pad; and a ring layer of the second conductivity type surrounding the dopant layer of the first conductivity type and reaching the buried layer of the second conductivity type.Type: ApplicationFiled: March 22, 2005Publication date: October 20, 2005Inventors: Manabu Imahashi, Hiroyoshi Ogura, Masakatsu Nawate
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Patent number: 5142348Abstract: A lateral thyristor is provided which includes a semiconductor substrate of a first conductivity type, an epitaxial layer of a second conductivity type formed on the semiconductor substrate, an anode diffusion layer of the first conductivity type formed in the epitaxial layer, a gate diffusion layer of the first conductivity type formed in the epitaxial layer, and a buried layer of the second conductivity type formed below the anode diffusion layer and extending between the semiconductor substrate and the epitaxial layer, wherein there is a region directly below the anode diffusion layer where the anode diffusion layer and the buried layer do not overlap each other, when the lateral thyristor is looked down upon in a direction perpendicular to the principal surface of the semiconductor substrate.Type: GrantFiled: August 13, 1990Date of Patent: August 25, 1992Assignee: Matsushita Electronics CorporationInventors: Manabu Imahashi, Hironori Kamiya