Abstract: A photomask is provided which can have a large depth of focus even if four main features are annularly arranged at random. The photomask has four annularly arranged main features based on design information of a circuit feature to be formed on a wafer, and a sub-feature is laid at an intersection point of two diagonal lines of a quadrangle formed by four vertices inside the four main features in order to increase a depth of focus of an exposure feature. Therefore, the depth of focus can be increased even if the main features are not arranged at a constant pitch.

Abstract: A photomask is provided which can have a large depth of focus even if four main features are annularly arranged at random. The photomask has four annularly arranged main features based on design information of a circuit feature to be formed on a wafer, and a sub-feature is laid at an intersection point of two diagonal lines of a quadrangle formed by four vertices inside the four main features in order to increase a depth of focus of an exposure feature. Therefore, the depth of focus can be increased even if the main features are not arranged at a constant pitch.

Abstract: A photomask is disclosed which can suppress deterioration of the depth of focus even in the case where main features are arranged randomly. Sub-features are replaced by a quadrangular sub-feature located inside an external quadrangle which includes as part of its outer periphery the outermost portions of the original sub-features. The sub-feature after the replacement is preferably in a square shape and the length of one side thereof is determined in accordance with the length of the associated external quadrangle. A central position of the sub-feature after the replacement is preferably coincident with the center of the external quadrangle or the center of gravity of the region which includes the original sub-features.

Abstract: A photomask is disclosed which can suppress deterioration of the depth of focus even in the case where main features are arranged randomly. Sub-features are replaced by a quadrangular sub-feature located inside an external quadrangle which includes as part of its outer periphery the outermost portions of the original sub-features. The sub-feature after the replacement is preferably in a square shape and the length of one side thereof is determined in accordance with the length of the associated external quadrangle. A central position of the sub-feature after the replacement is preferably coincident with the center of the external quadrangle or the center of gravity of the region which includes the original sub-features.

Abstract: An apparatus for determining the optimum size of a LSI chip of the present invention has the-theoretical-number-of-chips calculating means 5 calculating the theoretical number of chips according to a chip configuration in a mask calculated by in-the-mask-chip-configuration calculating means 3 and the information of wafer-line information holding part 4; the-number-of-transcriptions calculating means 6 calculating the number of transcriptions of a layout pattern on the mask to a wafer according to the chip configuration in the mask calculated by in-the-mask-chip configuration calculating means 3 and the theoretical number of chips calculated by the-theoretical-number-of-chips calculating means 5; and display part 9 that displays the calculated theoretical number of chips and number of transcriptions.

Abstract: A pattern data generating system solves a problem of a conventional pattern data generating system in which the total processing time is prolonged. The present pattern data generating system includes a parallel processing number calculator for computing the number of parallel processes to be used by a region divider that sequentially distributes the split pattern data. A group of pattern data generators generate pattern data in parallel processes. A pattern data combiner combines the pattern data output from the pattern data generators. A parallel processing controller controls the processing.

Abstract: A solid state imager is comprised of an imager unit composed of a plurality of sensitive units arrayed in the unit of pixels in a two-dimensional manner in the horizontal and vertical directions and vertical transfer units for transferring electric charges read-out from the sensitive units in the vertical direction at every vertical column, and a horizontal transfer unit formed of charge transfer unit group (8.sub.1, 8.sub.2, 8.sub.3, . . . ) of a plurality of bits in which a clock voltage (.phi..sub.H1) is applied to a first charge transfer unit group (8.sub.1, 8.sub.3. . . ) at every other bit including the charge transfer unit (8.sub.1) of a final bit and a clock voltage (.phi..sub.H2) is applied to a second charge transfer unit group (8.sub.2, 8.sub.4, . . . ) at every other bit of the remaining bit to transfer the electric charges supplied from the image unit in the horizontal direction, wherein a cross point between a leading edge of the clock voltage (.phi..sub.