Patents by Inventor Manabu Ishimatsu
Manabu Ishimatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9411015Abstract: Disclosed herein is a device that includes a semiconductor substrate, a check circuit and a through-substrate via. The check circuit includes a check line formed over the semiconductor substrate and including first and second parts each extending in a first direction and a third part extending in a second direction that crosses the first direction, the first and second parts being opposite to each other, the third part connecting one end of the first part with one end of the second part, a charge circuit coupled to a one end of the check line, and a comparator coupled to the other end of the check line at a first input node thereof. The through-substrate via penetrates through the semiconductor substrate and is located in an area that is between the first and second parts of the check line.Type: GrantFiled: March 14, 2013Date of Patent: August 9, 2016Assignee: PS4 Luxco S.a.r.l.Inventors: Hideyuki Yokou, Manabu Ishimatsu, Naoki Ogawa
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Patent number: 9379600Abstract: Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.Type: GrantFiled: February 6, 2014Date of Patent: June 28, 2016Assignee: PS4 Luxco S.a.r.l.Inventors: Hideyuki Yokou, Isao Nakamura, Manabu Ishimatsu
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Patent number: 9368189Abstract: A semiconductor device includes an output circuit having a plurality of unit buffer circuits, an impedance of each unit buffer circuit of the plurality of unit buffer circuits being adjustable, a control circuit configured to selectively activate one or more unit buffer circuits of the plurality of unit buffer circuits, and an impedance adjustment unit configured to adjust the impedance of each of the unit buffer circuits of the plurality of unit buffer circuits. The impedance adjustment unit includes a first power line, a replica circuit, and a load current generation circuit. The replica circuit and the load current generation circuit are coupled in common to the first power line, the replica circuit has a replica impedance that is substantially equal to the impedance of the output circuit, and the load current generation circuit changes current flowing therethrough.Type: GrantFiled: June 3, 2014Date of Patent: June 14, 2016Assignee: PS4 LUXCO S.A.R.L.Inventors: Hideyuki Yokou, Koji Uemura, Manabu Ishimatsu
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Patent number: 9252062Abstract: A method for manufacturing a stacked semiconductor memory device includes testing a plurality of memory chips to detect first defective addresses, programming optical fuses with first defective address information on each of the plurality of memory chips that have the first defective addresses, stacking the plurality of memory chips, testing the stacked memory chips to detect second defective addresses, and programming electrical fuses with second defective address information.Type: GrantFiled: January 23, 2014Date of Patent: February 2, 2016Assignee: PS4 Luxco S.a.r.l.Inventors: Akira Ide, Manabu Ishimatsu, Kentaro Hara
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Publication number: 20140286109Abstract: A semiconductor device includes an output circuit having a plurality of unit buffer circuits, an impedance of each unit buffer circuit of the plurality of unit buffer circuits being adjustable, a control circuit configured to selectively activate one or more unit buffer circuits of the plurality of unit buffer circuits, and an impedance adjustment unit configured to adjust the impedance of each of the unit buffer circuits of the plurality of unit buffer circuits. The impedance adjustment unit includes a first power line, a replica circuit, and a load current generation circuit. The replica circuit and the load current generation circuit are coupled in common to the first power line, the replica circuit has a replica impedance that is substantially equal to the impedance of the output circuit, and the load current generation circuit changes current flowing therethrough.Type: ApplicationFiled: June 3, 2014Publication date: September 25, 2014Inventors: Hideyuki YOKOU, Koji UEMURA, Manabu ISHIMATSU
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Patent number: 8766664Abstract: The semiconductor device comprises an output circuit that includes a plurality of unit buffer circuits each of which has an adjustable impedance, a control circuit that selectively activates one or ones of the unit buffer circuits, and an impedance adjustment unit that adjusts the impedances of the unit buffer circuits and includes a power line, a replica circuit, which has a replica impedance that is substantially equal to the adjustable impedance of each of the unit buffer circuits, and a load current generation circuit, which changes current flowing therethrough in accordance with the number of activated the one or ones of the unit buffer circuits. The replica circuit and the load current generation circuit are connected in common to the power line.Type: GrantFiled: October 10, 2012Date of Patent: July 1, 2014Inventors: Hideyuki Yokou, Koji Uemura, Manabu Ishimatsu
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Publication number: 20140152380Abstract: Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.Type: ApplicationFiled: February 6, 2014Publication date: June 5, 2014Applicant: Elpida Memory, Inc.Inventors: Hideyuki YOKOU, Isao NAKAMURA, Manabu ISHIMATSU
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Publication number: 20140141543Abstract: A method for manufacturing a stacked semiconductor memory device includes testing a plurality of memory chips to detect first defective addresses, programming optical fuses with first defective address information on each of the plurality of memory chips that have the first defective addresses, stacking the plurality of memory chips, testing the stacked memory chips to detect second defective addresses, and programming electrical fuses with second defective address information.Type: ApplicationFiled: January 23, 2014Publication date: May 22, 2014Inventors: Akira Ide, MANABU ISHIMATSU, KENTARO HARA
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Patent number: 8665008Abstract: Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.Type: GrantFiled: February 16, 2012Date of Patent: March 4, 2014Assignee: Elpida Memory, Inc.Inventors: Hideyuki Yokou, Isao Nakamura, Manabu Ishimatsu
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Patent number: 8644086Abstract: A semiconductor device includes a plurality of first chips, a second chip that controls the first chips, and internal wiring that connects the first chips and the second chip. The first chips each include: an optical fuse; a first latch circuit that retains information on the optical fuse; a second latch circuit that retains information on an electrical fuse, the information being supplied from the second chip through the internal wiring; and a select circuit that selects the information retained in either one of the first and second latch circuits. A redundancy determination signal is generated from the information selected. The information on the electrical fuse is transferred from the second chip to the first chips through the internal wiring.Type: GrantFiled: September 16, 2011Date of Patent: February 4, 2014Assignee: Elpida Memory, Inc.Inventors: Akira Ide, Manabu Ishimatsu, Kentaro Hara
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Publication number: 20130249578Abstract: Disclosed herein is a device that includes a semiconductor substrate, a check circuit and a through-substrate via. The check circuit includes a check line formed over the semiconductor substrate and including first and second parts each extending in a first direction and a third part extending in a second direction that crosses the first direction, the first and second parts being opposite to each other, the third part connecting one end of the first part with one end of the second part, a charge circuit coupled to a one end of the check line, and a comparator coupled to the other end of the check line at a first input node thereof. The through-substrate via penetrates through the semiconductor substrate and is located in an area that is between the first and second parts of the check line.Type: ApplicationFiled: March 14, 2013Publication date: September 26, 2013Applicant: Elpida Memory, Inc.Inventors: Hideyuki YOKOU, Manabu ISHIMATSU, Naoki OGAWA
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Patent number: 8390318Abstract: Disclosed herein is a device that includes a replica buffer circuit that drives a calibration terminal, a reference-potential generating circuit that generates a reference potential, a comparison circuit that compares a potential appearing at the calibration terminal with the reference potential, and a control circuit that changes an output impedance of the replica buffer circuit based on a result of a comparison by the comparison circuit. The reference-potential generating circuit includes a first potential generating unit activated in response to an enable signal and a second potential generating unit activated regardless of the enable signal, and an output node of the first potential generating unit and an output node of the second potential generating unit are commonly connected to the comparison circuit.Type: GrantFiled: February 21, 2012Date of Patent: March 5, 2013Assignee: Elpida Memory, Inc.Inventors: Hideyuki Yokou, Takanori Eguchi, Manabu Ishimatsu
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Publication number: 20120212286Abstract: Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.Type: ApplicationFiled: February 16, 2012Publication date: August 23, 2012Applicant: Elpida Memory, Inc.Inventors: Hideyuki YOKOU, Isao Nakamura, Manabu Ishimatsu
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Publication number: 20120212254Abstract: Disclosed herein is a device that includes a replica buffer circuit that drives a calibration terminal, a reference-potential generating circuit that generates a reference potential, a comparison circuit that compares a potential appearing at the calibration terminal with the reference potential, and a control circuit that changes an output impedance of the replica buffer circuit based on a result of a comparison by the comparison circuit. The reference-potential generating circuit includes a first potential generating unit activated in response to an enable signal and a second potential generating unit activated regardless of the enable signal, and an output node of the first potential generating unit and an output node of the second potential generating unit are commonly connected to the comparison circuit.Type: ApplicationFiled: February 21, 2012Publication date: August 23, 2012Applicant: Elpida Memory, Inc.Inventors: Hideyuki YOKOU, Takanori Eguchi, Manabu Ishimatsu
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Publication number: 20120069685Abstract: A semiconductor device includes a plurality of first chips, a second chip that controls the first chips, and internal wiring that connects the first chips and the second chip. The first chips each include: an optical fuse; a first latch circuit that retains information on the optical fuse; a second latch circuit that retains information on an electrical fuse, the information being supplied from the second chip through the internal wiring; and a select circuit that selects the information retained in either one of the first and second latch circuits. A redundancy determination signal is generated from the information selected. The information on the electrical fuse is transferred from the second chip to the first chips through the internal wiring.Type: ApplicationFiled: September 16, 2011Publication date: March 22, 2012Applicants: Hitachi ULSI Systems Co., Ltd., Elpida Memory, Inc.Inventors: Akira Ide, Manabu Ishimatsu, Kentaro Hara
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Patent number: 6898110Abstract: In a device including regular circuits and redundant circuits, a plurality of relievable first wiring lines and a plurality of irrelievable second wiring lines are arranged in the same wiring layer as what constitutes the regular circuits and in the same direction, and at the same time the irrelievable wiring lines are arranged adjoining one another.Type: GrantFiled: October 19, 2001Date of Patent: May 24, 2005Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co. Ltd.Inventors: Manabu Ishimatsu, Yoshihiko Inoue, Hiroshi Yoshioka, Masahito Suzuki
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Publication number: 20040026716Abstract: Regular circuits and redundant circuits are provided, a plurality of relievable first wiring lines and a plurality of irrelievable second wiring lines are arranged in the same wiring layer as what constitutes the regular circuits and in the same direction, and at the same time the irrelievable wiring lines are arranged adjoining one another.Type: ApplicationFiled: May 14, 2003Publication date: February 12, 2004Inventors: Manabu Ishimatsu, Yoshihiko Inoue, Hiroshi Yoshioka, Masahito Suzuki
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Patent number: 6504770Abstract: There is provided a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved. The inventive semiconductor memory is a 64 M-bits or 256 M-bits DRAM using a hierarchical word line structure or a multi-division bit line structure and comprises a main row decoder region, a main word driver region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a sub-word driver region, intersection regions and the like formed on one semiconductor chip.Type: GrantFiled: February 7, 2002Date of Patent: January 7, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Goro Kitsukawa, Toshitsugu Ueda, Manabu Ishimatsu, Michihiro Mishima
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Patent number: 6407952Abstract: There is provided a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved. The inventive semiconductor memory is a 64 M-bits or 256 M-bits DRAM using a hierarchical word line structure or a multi-division bit line structure and comprises a main row decoder region, a main word driver region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a sub-word driver region, intersection regions and the like formed on one semiconductor chip.Type: GrantFiled: November 21, 2000Date of Patent: June 18, 2002Assignees: Hitachi, Ltd., Hitachi USLI Systems Co., Ltd.Inventors: Goro Kitsukawa, Toshitsugu Ueda, Manabu Ishimatsu, Michihiro Mishima
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Publication number: 20020071324Abstract: There is provided a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved. The inventive semiconductor memory is a 64 M-bits or 256 M-bits DRAM using a hierarchical word line structure or a multi-division bit line structure and comprises a main row decoder region, a main word driver region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a sub-word driver region, intersection regions and the like formed on one semiconductor chip.Type: ApplicationFiled: February 7, 2002Publication date: June 13, 2002Inventors: Goro Kitsukawa, Toshitsugu Ueda, Manabu Ishimatsu, Michihiro Mishima