Patents by Inventor Manabu Kitano

Manabu Kitano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device
    Publication number: 20040219727
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS•FETs.
    Type: Application
    Filed: June 7, 2004
    Publication date: November 4, 2004
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
  • Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device
    Patent number: 6806130
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS·FETs.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: October 19, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
  • Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device
    Patent number: 6630375
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS·FETs.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: October 7, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
  • Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device
    Publication number: 20020061615
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer The well region is formed with the gate insulating films of MIS·FETs.
    Type: Application
    Filed: December 14, 2001
    Publication date: May 23, 2002
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
  • Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device
    Publication number: 20020055204
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETS.
    Type: Application
    Filed: December 5, 2001
    Publication date: May 9, 2002
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
  • Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device
    Patent number: 6368905
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.
    Type: Grant
    Filed: February 25, 2000
    Date of Patent: April 9, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
  • Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device
    Patent number: 6043114
    Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: March 28, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa