Abstract: A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.

Abstract: A semiconductor device performs a software lock-step. The semiconductor device includes a first circuit group including a first Intellectual Property (IP) to be operated in a first address space, a first bus, and a first memory, a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory, a third bus connectable to a third memory, and a transfer control circuit coupled to the first to third buses. when the software lock-step is performed, the second circuit group converts an access address from the second IP to the second memory such that an address assigned to the second memory in the second address space is a same as an address assigned to the first memory in the first address space.

Abstract: A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.

Abstract: A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.

Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

Abstract: A semiconductor apparatus pertaining to one embodiment has: a first processor that operates by a first program and reads pixel data from a storage unit; a second processor that operates by a second program, performs processing to the pixel data, and writes the processed pixel data back to the storage unit; and a buffer circuit that transfers the pixel data from the first processor to the second processor.

Abstract: An image processing apparatus includes: a first memory that stores image data; a second memory that can be accessed at a speed higher than that in an access to the first memory; a first operation unit that executes a predetermined task on a predetermined area of the image data transferred from the first memory to the second memory; a second operation unit that determines whether there is an overlapping part of a first area of the image data executed corresponding to a first task executed by the first operation unit and a second area of the image data executed corresponding to a second task different from the first task; and a memory control apparatus that controls the first memory and the second memory. The memory control apparatus performs control to reuse the image data in the second memory when it is determined that there is an overlapping part.

Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

Abstract: A semiconductor apparatus pertaining to one embodiment has: a first processor that operates by a first program and reads pixel data from a storage unit; a second processor that operates by a second program, performs processing to the pixel data, and writes the processed pixel data back to the storage unit; and a buffer circuit that transfers the pixel data from the first processor to the second processor.

Abstract: As a basic managing pattern, each manufacturing lot containing at least one workpiece is designated as a main objective to be managed. An appropriate number of similar type manufacturing lots containing workpieces having the same work conditions in at least one work step are loaded on a carrier. Then, the carrier is transported to a batch apparatus that performs simultaneous processing or machining operation applied to the workpieces or to an apparatus that brings the workpieces into an in-process work step under the same conditions, so as to cause the workpieces contained in respective similar type manufacturing lots to pass along a plurality of manufacturing process flows. Alternatively, an appropriate number of different type manufacturing lots containing workpieces having different work conditions are loaded on a carrier.

Abstract: As a basic managing pattern, each manufacturing lot containing at least one workpiece is designated as a main objective to be managed. An appropriate number of similar type manufacturing lots containing workpieces having the same work conditions in at least one work step are loaded on a carrier. Then, the carrier is transported to a batch apparatus that performs simultaneous processing or machining operation applied to the workpieces or to an apparatus that brings the workpieces into an in-process work step under the same conditions, so as to cause the workpieces contained in respective similar type manufacturing lots to pass along a plurality of manufacturing process flows. Alternatively, an appropriate number of different type manufacturing lots containing workpieces having different work conditions are loaded on a carrier.

Abstract: In a method of manufacturing a semiconductor device, after performing ion-implantation and before forming an oxide film, a silicon substrate is disposed within a furnace to undergo a heat treatment at a temperature equal to or higher than 950° C. for a specific time period (equal to or longer than 15 minutes). When performing the heat treatment and when raising a temperature up to the heat treatment temperature, oxygen is supplied together with nitrogen gas (inert gas). A supply amount of oxygen is controlled to be equal to or less than 5% when raising the temperature up to the heat treatment temperature, and to be equal to or less than 2% when performing the heat treatment. After the heat treatment, the oxidation film is formed. As a result, crystal defects (OSFs) are prevented from being produced on the silicon substrate surface.

Abstract: On the surface of a semiconductor substrate there are formed a silicon oxide film, silicon nitride film and resist, whereby a groove is formed in the semiconductor substrate through an opening portion by chemical dry etching. An oxide film is formed on the inner surface of the groove by wet oxidation and, further, this oxide film is removed by wet etching, after which the surface of the semiconductor substrate located on the outer-peripheral side of the groove from an angular portion defined between a side surface of the groove and the surface of the semiconductor substrate is exposed. Then, the inner surface of the groove and the exposed surface of the semiconductor substrate are oxidized to thereby form a LOCOS oxide film, and thereafter this LOCOS oxide film is removed. As a result of this, the angular portion is made round, thereby enabling the avoidance of the concentration of an electric field on the angular portion of the groove.

Abstract: A surface of a non-magnetic base plate is first coarsened to a required surface roughness and an ultrasonic vibration is then applied to the surface of the non-magnetic base plate while the nonmagnetic base plate is immersed in a liquid. Thereafter, a magnetic recording layer and a protective layer are successively formed on the surface of the non-magnetic base plate thereby to produce a magnetic recording medium. It is preferable that the frequency of a ultrasonic is within a range from 200 kHz to 1600 kHz. Surface fractional properties of the magnetic recording medium can adequately be controlled without variation of floatation height of a magnetic head during its running by varying an ultrasonic oscillation output and an ultrasonic processing time.

Abstract: The second harmonic wave of a solid laser light which is emitted from a second harmonic wave light source is divided into a plurality of laser beams by a diffraction grating. The divided laser beams are converged on a record carrier into a plurality of light spots by an optical head. Magnetic field generating coils for applying magnetic fields to the respective light spots in accordance with the recording signals from a signal line are disposed under the record carrier. Part of the solid laser light is reflected and input to a beam splitter. Since part of the light input to the beam splitter is taken out, a stabilizer controls the output of the solid laser light from the second harmonic wave light source, parallel recording/reproduction using the plurality of light spots which are arranged on the record carrier is enabled and the formation of the plurality of light spots is effectively controlled.

Abstract: An optical recording apparatus which reduces light loss by expanding the laser beam diameters irradiated from a plurality of beam sources, and reducing the expanded beam diameters immediately before focusing the beams onto an information recording/reproducing medium to make the beams circular, thereby minimizing deviation of the laser beam from the optical axis.An optical system for use in recording apparatus with a multi-beam optical head provided with a plurality of laser beam sources in a fixed unit which reduces light loss by minimizing deviation of the laser beam from the optical axis, and also by maintaining the laser power of each laser beam at a predetermined intensity independent of changes in distance between the fixed unit half and the moving unit half of the optical system by detecting intensities of the laser beams focused on a recording medium.

Abstract: An optical recording apparatus which reduces light loss by expanding the laser beam diameters irradiated from a plurality of beam sources, and reducing the expanded beam diameters immediately before focusing the beams onto an information recording medium to make the beams circular, thereby minimizing deviation of the laser beam from the optical axis. An optical system for use in recording apparatus with a multi-beam optical head provided with a plurality of laser beam sources in a fixed unit which reduces light loss by minimizing deviation of the laser beam from the optical axis, and also by maintaining the laser power of each laser beam at a predetermined intensity independent of changes in distance between the fixed unit half and the moving unit half of the optical system by detecting intensities of the laser beams focused on a recording medium.