Patents by Inventor Manabu Kudo

Manabu Kudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12279751
    Abstract: An image fiber includes: a plurality of cores; a cladding that integrally encloses the plurality of cores; a light guide fiber that propagates illumination light; and a light guide layer that covers an entire periphery of an external peripheral surface of the cladding and that is in contact with an external peripheral surface of the light guide fiber. The light guide layer is capable of propagating the illumination light.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: April 22, 2025
    Assignee: Fujikura Ltd.
    Inventors: Masami Miyachi, Manabu Kudo
  • Patent number: 12224556
    Abstract: The light emitting device includes a substrate, and a laminated structure including columnar parts, wherein the columnar parts include a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer, the light emitting layer has a c-plane and a facet plane, the second semiconductor layer is disposed on the c-plane and the facet plane, the first semiconductor layer has a first portion and a second portion smaller in diametrical size than the first portion, the second portion is disposed between the substrate and the first portion, and the c-plane and the second portion overlap each other, and the c-plane is smaller in diametrical size than the second portion in a plan view from a stacking direction of the first semiconductor layer and the light emitting layer.
    Type: Grant
    Filed: March 13, 2022
    Date of Patent: February 11, 2025
    Assignees: SEIKO EPSON CORPORATION, SOPHIA SCHOOL CORPORATION
    Inventors: Manabu Kudo, Katsumi Kishino
  • Publication number: 20220294184
    Abstract: The light emitting device includes a substrate, and a laminated structure including columnar parts, wherein the columnar parts include a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer, the light emitting layer has a c-plane and a facet plane, the second semiconductor layer is disposed on the c-plane and the facet plane, the first semiconductor layer has a first portion and a second portion smaller in diametrical size than the first portion, the second portion is disposed between the substrate and the first portion, and the c-plane and the second portion overlap each other, and the c-plane is smaller in diametrical size than the second portion in a plan view from a stacking direction of the first semiconductor layer and the light emitting layer.
    Type: Application
    Filed: March 13, 2022
    Publication date: September 15, 2022
    Applicants: SEIKO EPSON CORPORATION, SOPHIA SCHOOL CORPORATION
    Inventors: Manabu KUDO, Katsumi KISHINO
  • Publication number: 20220257098
    Abstract: An image fiber includes: a plurality of cores; a cladding that integrally encloses the plurality of cores; a light guide fiber that propagates illumination light; and a light guide layer that covers an entire periphery of an external peripheral surface of the cladding and that is in contact with an external peripheral surface of the light guide fiber. The light guide layer is capable of propagating the illumination light.
    Type: Application
    Filed: June 25, 2020
    Publication date: August 18, 2022
    Applicant: Fujikura Ltd.
    Inventors: Masami Miyachi, Manabu Kudo
  • Publication number: 20180331230
    Abstract: A semiconductor device includes a substrate, a thin film transistor, and an insulating film that is provided between the substrate and the thin film transistor, in which the insulating film includes a first silicon oxide film, a silicon nitride film that is formed on the first silicon oxide film, and a second silicon oxide film that is formed on the silicon nitride film, and the nitrogen concentration in the first silicon oxide film is lower than that in the second silicon oxide film.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 15, 2018
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Manabu KUDO
  • Patent number: 10032941
    Abstract: A method of manufacturing a photoelectric conversion element including a semiconductor layer includes: forming an electrode; forming an insulating layer covering the electrode; forming an opening in a region of the insulating layer overlapping the electrode in a plan view; forming a covering layer of a semiconductor material on a surface of the insulating layer; and forming the semiconductor layer by patterning the covering layer. In the forming of the semiconductor layer, the semiconductor layer is formed such that an outer circumferential edge of the semiconductor layer is located on the outside of an inner circumferential edge of the opening in the plan view.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: July 24, 2018
    Assignee: Seiko Epson Corporation
    Inventor: Manabu Kudo
  • Patent number: 9876049
    Abstract: An image sensor as a photoelectric conversion device includes: a lower electrode containing a high-melting-point metal; an upper electrode disposed in a layer higher than the lower electrode; a p-type semiconductor layer and an n-type semiconductor layer disposed between the lower electrode and the upper electrode; and a relay electrode containing the high-melting-point metal. The lower electrode and the relay electrode are formed in the same layer. An intermediate layer as a selenized film of the high-melting-point metal is formed on the lower electrode.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: January 23, 2018
    Assignee: Seiko Epson Corporation
    Inventor: Manabu Kudo
  • Publication number: 20170179311
    Abstract: A method of manufacturing a photoelectric conversion element including a semiconductor layer includes: forming an electrode; forming an insulating layer covering the electrode; forming an opening in a region of the insulating layer overlapping the electrode in a plan view; forming a covering layer of a semiconductor material on a surface of the insulating layer; and forming the semiconductor layer by patterning the covering layer. In the forming of the semiconductor layer, the semiconductor layer is formed such that an outer circumferential edge of the semiconductor layer is located on the outside of an inner circumferential edge of the opening in the plan view.
    Type: Application
    Filed: November 29, 2016
    Publication date: June 22, 2017
    Inventor: Manabu KUDO
  • Patent number: 9614115
    Abstract: Provided is a semiconductor device that can suppress a leakage current more than has been achieved before. A semiconductor device 22 includes a first carrier holding layer 48, which is arranged on a lower electrode 47, is in contact with a lower electrode 47 via a first interface 49, and includes majority carriers of one type, and a second carrier holding layer 57, which is arranged on the first carrier holding layer 48, defines a second interface 58 constituting a conduction path to the first carrier holding layer 48, and includes majority carriers of the other type. The first interface 49 has its outline within the outline of the first carrier holding layer 48 when seen in a plan view in a direction that is orthogonal to a surface of the substrate, and the second interface 58 has its outline within the outline of the first carrier holding layer 48 when seen in the plan view.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: April 4, 2017
    Assignee: Seiko Epson Corporation
    Inventor: Manabu Kudo
  • Publication number: 20160163761
    Abstract: An image sensor as a photoelectric conversion device includes: a lower electrode containing a high-melting-point metal; an upper electrode disposed in a layer higher than the lower electrode; a p-type semiconductor layer and an n-type semiconductor layer disposed between the lower electrode and the upper electrode; and a relay electrode containing the high-melting-point metal. The lower electrode and the relay electrode are formed in the same layer. An intermediate layer as a selenized film of the high-melting-point metal is formed on the lower electrode.
    Type: Application
    Filed: November 24, 2015
    Publication date: June 9, 2016
    Inventor: Manabu KUDO
  • Publication number: 20150102449
    Abstract: Provided is a semiconductor device that can suppress a leakage current more than has been achieved before. A semiconductor device 22 includes a first carrier holding layer 48, which is arranged on a lower electrode 47, is in contact with a lower electrode 47 via a first interface 49, and includes majority carriers of one type, and a second carrier holding layer 57, which is arranged on the first carrier holding layer 48, defines a second interface 58 constituting a conduction path to the first carrier holding layer 48, and includes majority carriers of the other type. The first interface 49 has its outline within the outline of the first carrier holding layer 48 when seen in a plan view in a direction that is orthogonal to a surface of the substrate, and the second interface 58 has its outline within the outline of the first carrier holding layer 48 when seen in the plan view.
    Type: Application
    Filed: October 1, 2014
    Publication date: April 16, 2015
    Inventor: Manabu KUDO
  • Patent number: 9006017
    Abstract: A circuit layer is formed on a surface of a substrate and includes a transistor. A photoelectric conversion element includes a photoelectric conversion layer of a chalcopyrite-type semiconductor provided between a first electrode and a second electrode. A supply layer is formed between the circuit layer and the photoelectric conversion layer and contains an Ia group element. Diffusion of the Ia group element to the photoelectric conversion layer improves the photoelectric conversion efficiency. A protective layer is formed between the supply layer and the circuit layer and prevents the diffusion of the Ia group element to the circuit layer.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: April 14, 2015
    Assignee: Seiko Epson Corporation
    Inventor: Manabu Kudo
  • Publication number: 20150011041
    Abstract: A circuit layer is formed on a surface of a substrate and includes a transistor. A photoelectric conversion element includes a photoelectric conversion layer of a chalcopyrite-type semiconductor provided between a first electrode and a second electrode. A supply layer is formed between the circuit layer and the photoelectric conversion layer and contains an Ia group element. Diffusion of the Ia group element to the photoelectric conversion layer improves the photoelectric conversion efficiency. A protective layer is formed between the supply layer and the circuit layer and prevents the diffusion of the Ia group element to the circuit layer.
    Type: Application
    Filed: September 22, 2014
    Publication date: January 8, 2015
    Inventor: Manabu KUDO
  • Patent number: 8883537
    Abstract: A circuit layer is formed on a surface of a substrate and includes a transistor. A photoelectric conversion element includes a photoelectric conversion layer of a chalcopyrite-type semiconductor provided between a first electrode and a second electrode. A supply layer is formed between the circuit layer and the photoelectric conversion layer and contains an Ia group element. Diffusion of the Ia group element to the photoelectric conversion layer improves the photoelectric conversion efficiency. A protective layer is formed between the supply layer and the circuit layer and prevents the diffusion of the Ia group element to the circuit layer.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: November 11, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Manabu Kudo
  • Publication number: 20120241894
    Abstract: A circuit layer is formed on a surface of a substrate and includes a transistor. A photoelectric conversion element includes a photoelectric conversion layer of a chalcopyrite-type semiconductor provided between a first electrode and a second electrode. A supply layer is formed between the circuit layer and the photoelectric conversion layer and contains an Ia group element. Diffusion of the Ia group element to the photoelectric conversion layer improves the photoelectric conversion efficiency. A protective layer is formed between the supply layer and the circuit layer and prevents the diffusion of the Ia group element to the circuit layer.
    Type: Application
    Filed: March 16, 2012
    Publication date: September 27, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Manabu KUDO
  • Patent number: 7160768
    Abstract: The invention provides a semiconductor device, which removes troubles occurring when the parasitic capacitance between layered wiring lines with an interlayer insulating film therebetween is reduced, and have a simple structure and high reliability. The electronic device according to the invention can include a semiconductor layer formed on a substrate, a gate insulating layer formed on the semiconductor layer, a gate electrode having a predetermined pattern and formed on the gate insulating layer, an interlayer insulating film formed to cover the gate electrode, a source electrode and a drain electrode formed on the interlayer insulating film. The interlayer insulating film can be mainly made of silicon oxynitride with a nitrogen concentration of atomic percent or higher.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: January 9, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Manabu Kudo, Osamu Ohara
  • Publication number: 20050029593
    Abstract: The invention provides a semiconductor device, which removes troubles occurring when the parasitic capacitance between layered wiring lines with an interlayer insulating film therebetween is reduced, and have a simple structure and high reliability. The electronic device according to the invention can include a semiconductor layer formed on a substrate, a gate insulating layer formed on the semiconductor layer, a gate electrode having a predetermined pattern and formed on the gate insulating layer, an interlayer insulating film formed to cover the gate electrode, a source electrode and a drain electrode formed on the interlayer insulating film. The interlayer insulating film can be mainly made of silicon oxynitride with a nitrogen concentration of atomic percent or higher.
    Type: Application
    Filed: July 8, 2004
    Publication date: February 10, 2005
    Applicant: Seiko Epson Corporation
    Inventors: Manabu Kudo, Osamu Ohara