Patents by Inventor Manabu Nakago

Manabu Nakago has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5543996
    Abstract: An overheat protective circuit includes a first voltage generator generating a first voltage stabilized against a change of an operating temperature, a second voltage generator generating a second voltage changeable in accordance with a change of the operating temperature, a comparator having first and second inputs coupled to receive the first and second voltages, respectively, and a switching circuit responding to a first logic level of the output signal from the comparator to render a transistor to be protected non-conductive. This protective circuit further includes a control circuit which monitors a power voltage and controls, when the power voltage is in a predetermined range, the level at one of the first and second inputs of the comparator such that the comparator outputs its output signal having the second logic level to deactivate the switching circuit.
    Type: Grant
    Filed: December 27, 1994
    Date of Patent: August 6, 1996
    Assignee: NEC Corporation
    Inventor: Manabu Nakago
  • Patent number: 5384529
    Abstract: A current limiting circuit which includes a vertical MOS transistor as an output transistor has a clamping voltage that can be established with high accuracy, and once established, is less dependent on temperature. The gate of an output N-channel VDMOS transistor is connected to a constant-voltage circuit composed of an N-channel VDMOS transistor having the same characteristics as those of the output N-channel VDMOS transistor and two series-connected resistors which supply a divided voltage to the gate of the N-channel VDMOS transistor. The clamping voltage between the gate and source of the output N-channel VDMOS transistor can be adjusted based on the voltage divided by the resistors of the constant-voltage circuit. The temperature characteristics of the output N-channel VDMOS transistor and the constant-voltage circuit are held in phase with each other to reduce variations in the clamping voltage caused by temperature variations.
    Type: Grant
    Filed: January 28, 1994
    Date of Patent: January 24, 1995
    Assignee: NEC Corporation
    Inventor: Manabu Nakago