Abstract: An output circuit includes a first switch that outputs a positive voltage signal received via a first node when in an ON state, a second switch that outputs a negative voltage signal received via a second node when in an ON state, third and fourth switches that set the first and second nodes to a reference power supply voltage when in an ON state, a first follower circuit that generates, as a gate voltage, a voltage signal following and being in phase with a voltage signal of the first node through source follower operation and supplies the gate voltage to a gate of the first switch, and a second follower circuit that generates, as a gate voltage, a voltage signal following and being in phase with a voltage signal of the second node through source follower operation and supplies the gate voltage to a gate of the second switch.

Abstract: An output circuit includes a first switch that outputs a positive voltage signal received via a first node when in an ON state, a second switch that outputs a negative voltage signal received via a second node when in an ON state, third and fourth switches that set the first and second nodes to a reference power supply voltage when in an ON state, a first follower circuit that generates, as a gate voltage, a voltage signal following and being in phase with a voltage signal of the first node through source follower operation and supplies the gate voltage to a gate of the first switch, and a second follower circuit that generates, as a gate voltage, a voltage signal following and being in phase with a voltage signal of the second node through source follower operation and supplies the gate voltage to a gate of the second switch.

Abstract: A level voltage generation circuit, a data driver and a display are provided. The level voltage generation circuit generates, based on N different input voltages, M (M>N) level voltages. The level voltage generation circuit comprises N differential amplifiers having output ends, which receive the N input voltages respectively, amplify the N input voltages respectively and output amplified N input voltages, and a resistor ladder having N voltage supply points respectively connected to the output ends of the N differential amplifiers and M voltage output points for outputting the M level voltages. The resistor ladder comprises a first wiring, connected to the output end of one of the N differential amplifiers through one of the N voltage supply points; and a second wiring, connected between one of the M voltage output points and one of an input pair of one of the N differential amplifiers.

Abstract: A level voltage generation circuit, a data driver and a display are provided. The level voltage generation circuit generates, based on N different input voltages, M (M>N) level voltages. The level voltage generation circuit comprises N differential amplifiers having output ends, which receive the N input voltages respectively, amplify the N input voltages respectively and output amplified N input voltages, and a resistor ladder having N voltage supply points respectively connected to the output ends of the N differential amplifiers and M voltage output points for outputting the M level voltages. The resistor ladder comprises a first wiring, connected to the output end of one of the N differential amplifiers through one of the N voltage supply points; and a second wiring, connected between one of the M voltage output points and one of an input pair of one of the N differential amplifiers.

Abstract: The display apparatus includes: N differential amplifiers having output ends, amplifying N input voltages and outputting amplified voltages, and a resistor ladder having N voltage supply points connected to the output ends of the N differential amplifiers and M voltage output points outputting M level voltages. The M voltage output points are connected to capacitive loads on input sides of the amplifiers, and at least one N differential amplifier has an input pair and an output end connected to one of the N voltage supply point. One of the N input voltages is received by one of the input pair, the other one of the input pair is connected to one of the M voltage output points outputting a level voltage closest to a voltage at the one voltage supply point. The one voltage supply point and the one voltage output point are at different positions on the resistor ladder.

Abstract: The display apparatus includes: N differential amplifiers having output ends, amplifying N input voltages and outputting amplified voltages, and a resistor ladder having N voltage supply points connected to the output ends of the N differential amplifiers and M voltage output points outputting M level voltages. The M voltage output points are connected to capacitive loads on input sides of the amplifiers, and at least one N differential amplifier has an input pair and an output end connected to one of the N voltage supply point. One of the N input voltages is received by one of the input pair, the other one of the input pair is connected to one of the M voltage output points outputting a level voltage closest to a voltage at the one voltage supply point. The one voltage supply point and the one voltage output point are at different positions on the resistor ladder.

Abstract: A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.

Abstract: A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.

Abstract: A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.

Abstract: A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.

Abstract: An operational amplifier includes an output circuit and a differential circuit. The output circuit outputs a voltage in a voltage range determined either from a highest voltage that is an upper limit of a predetermined power source range, or from a lowest voltage that is a lower limit of the predetermined power source range, to an intermediate voltage that is a voltage between the highest voltage and the lowest voltage. The differential circuit includes a first MOS transistor to which a driving signal for driving a display panel is input and a second MOS transistor to which a given input signal is input. The first MOS transistor and the second MOS transistor are connected in parallel, and a differential input-permissible-range of the differential circuit is wider than the voltage range of the output circuit.

Abstract: The present disclosure provides a display panel driving apparatus that can make the circuit layout surface area smaller, and prevent circuit damage. The display panel driving apparatus includes a source amplifier, a sink amplifier, a switch and the like. The source amplifier includes a first output circuit, a second output circuit and the like, and a guard transistor is provided between the first output circuit and the second output circuit to prevent an output signal voltage of the first output circuit from becoming less than an intermediate voltage. The sink amplifier includes a first output circuit and a second output circuit, and a guard transistor is provided between the first output circuit and the second output circuit to prevent an output signal voltage of the first output circuit from exceeding an intermediate voltage.

Abstract: The present disclosure provides a display panel driving apparatus that can make the circuit layout surface area smaller, and prevent circuit damage. The display panel driving apparatus includes a source amplifier, a sink amplifier, a switch and the like. The source amplifier includes a first output circuit, a second output circuit and the like, and a guard transistor is provided between the first output circuit and the second output circuit to prevent an output signal voltage of the first output circuit from becoming less than an intermediate voltage. The sink amplifier includes a first output circuit and a second output circuit, and a guard transistor is provided between the first output circuit and the second output circuit to prevent an output signal voltage of the first output circuit from exceeding an intermediate voltage.

Abstract: An operational amplifier includes an output circuit and a differential circuit. The output circuit outputs a voltage in a voltage range determined either from a highest voltage that is an upper limit of a predetermined power source range, or from a lowest voltage that is a lower limit of the predetermined power source range, to an intermediate voltage that is a voltage between the highest voltage and the lowest voltage. The differential circuit includes a first MOS transistor to which a driving signal for driving a display panel is input and a second MOS transistor to which a given input signal is input. The first MOS transistor and the second MOS transistor are connected in parallel, and a differential input-permissible-range of the differential circuit is wider than the voltage range of the output circuit.

Abstract: External output terminal 28 is clamped by clamping circuit 20, and a current mirror is configured using diode circuit 23 within clamping circuit 20 and detector transistor 34. When the voltage of external output terminal 28 can no longer be maintained by the first current supply circuit 11 alone as load 27 increases, clamping circuit 20 shuts off, and detector transistor 34 shuts off. As detector transistor 34 shuts off, the second current supplying element 12 becomes conductive and supplies a current to load 27. Because the second current supplying element 12 is not operating during normal operation during which the current consumption by load 27 is low, the current consumption is low. In addition, because no amplifier is required, only a small number of elements are required.

Abstract: External output terminal 28 is clamped by clamping circuit 20, and a current mirror is configured using diode circuit 23 within clamping circuit 20 and detector transistor 34. When the voltage of external output terminal 28 can no longer be maintained by the first current supply circuit 11 alone as load 27 increases, clamping circuit 20 shuts off, and detector transistor 34 shuts off. As detector transistor 34 shuts off, the second current supplying element 12 becomes conductive and supplies a current to load 27. Because the second current supplying element 12 is not operating during normal operation during which the current consumption by load 27 is low, the current consumption is low. In addition, because no amplifier is required, only a small number of elements are required.

Abstract: A shift register with low power consumption has memory circuits 151-15N connected in series, gate circuits in memory circuits 152n−1 in the odd-numbered locations become conductive when clock signal CK is high, and gate circuits in memory circuits 152n in the even-numbered locations become conductive when clock signal CK is low, wherein data signals S input are latched for output when the gate circuits are shut off. The circuit configuration is simplified. The Shift register operates every one half of the cycle of clock signal CK, allowing the frequency of clock signal to be reduced by half, resulting in reduced power consumption.