Abstract: In a dynamic random access memory (DRAM), first and second output transistors form an NMOS-type tristate output buffer. Interposed between a gate electrode of the first output transistor and a data input/output terminal (DQ terminal) is an auxiliary transistor of which gate electrode is grounded and of which threshold voltage is lower than that of the first output transistor. Further interposed between the DQ terminal and a gate electrode of the second output transistor is another auxiliary transistor of which gate electrode is grounded and of which threshold voltage is lower than that of the second output transistor. Both auxiliary transistors lower gate voltages of both output transistors down to a negative voltage level such that both output transistors are maintained as cut off when a negative voltage is externally applied to the DQ terminal at the time of high impedance.