Patents by Inventor Manabu Sueyoshi

Manabu Sueyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110298097
    Abstract: A semiconductor device is provided wherein stacked semiconductor substrates are electrically coupled together in a satisfactory state by a conductor buried in the interior of a through hole. A first semiconductor substrate includes a substrate having main surfaces, further includes a semiconductor element formed within and over the substrate, a wiring coupled to the semiconductor element electrically, and a conductive layer formed in the interior of a through hole, the through hole extending through mutually confronting first and second main surfaces as the main surfaces of the substrate and reaching the wiring. The first semiconductor substrate and a second semiconductor substrate are stacked and the conductive layer is coupled to a wiring of the second semiconductor substrate electrically. In a second main surface of the conductive layer, a recess is formed around an end portion of the through hole so that a bottom wall surface of the recess is present in the interior of the substrate.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 8, 2011
    Inventors: Manabu Sueyoshi, Seiji Muranaka, Tomoryo Shono, Itaru Kanno