Abstract: A detection system includes: an obtainer that obtains image data generated based on an amount of light received by each of a plurality of pixels from a detection target and event data generated based on a change in an amount of light received by each of a plurality of pixels from the detection target; a processor that extracts, from the event data as auxiliary information, information to be used to assist in detecting the detection target from the image data; and a detector that detects the detection target or a state of the detection target based on at least the image data and the auxiliary information.

Abstract: A leg muscle strength estimation system includes: an obtainer that obtains an image including a user that is walking as a subject of the image; and an estimator that estimates a leg muscle strength of the user based on the obtained image.

Abstract: The vertical sync signal generator includes: a vertical sync signal separation circuit for separating a vertical sync signal of an input luminance signal and outputting the separated signal as a first vertical sync signal; an automatic frequency control circuit for generating a second vertical sync signal having a repeat frequency corresponding with an average repeat frequency of the first vertical sync signal and outputting the generated signal; a vertical sync signal phase detection circuit for detecting whether or not the first vertical sync signal has two different periods repeated alternately and outputting the detection result as a decision signal; and a selector for receiving the first and second vertical sync signals, selecting the first vertical sync signal when the decision signal indicates that the first vertical sync signal has two different periods repeated alternately and otherwise selecting the second vertical sync signal and outputting the selected signal.

Abstract: The vertical sync signal generator includes: a vertical sync signal separation circuit for separating a vertical sync signal of an input luminance signal and outputting the separated signal as a first vertical sync signal; an automatic frequency control circuit for generating a second vertical sync signal having a repeat frequency corresponding with an average repeat frequency of the first vertical sync signal and outputting the generated signal; a vertical sync signal phase detection circuit for detecting whether or not the first vertical sync signal has two different periods repeated alternately and outputting the detection result as a decision signal; and a selector for receiving the first and second vertical sync signals, selecting the first vertical sync signal when the decision signal indicates that the first vertical sync signal has two different periods repeated alternately and otherwise selecting the second vertical sync signal and outputting the selected signal.

Abstract: A DD converter circuit 109 for interpolating a digital video signal which is locked to a 14.3-MHz burst clock to convert the sampling data so as to be locked to a 13.5-NHz free-run clock, and a frame memory circuit 110 for writing a digital video signal which is output by the DD converter circuit 109 on the 14.3-MHz burst clock as well as reading the written digital video signal on a 13.5-MHz clock S112 are included. Therefore, a video signal processor which can realize the rate conversion of the digital video signal without using an analog PLL circuit can be provided.

Abstract: A DD converter circuit 109 for interpolating a digital video signal which is locked to a 14.3-MHz burst locked clock to convert the sampling data so as to be locked to a 13.5-NHz free-run clock, and a frame memory circuit 110 for writing a digital video signal which is output by the DD converter circuit 109 on the 14.3-MHz burst locked clock as well as reading the written digital video signal on a 13.5-MHz clock S112 are included. Therefore, a video signal processor which can realize the rate conversion of the digital video signal without using an analog PLL circuit can be provided.

Abstract: A driving apparatus for a liquid crystal display of a type sandwiching a layer of liquid crystal material capable of responding to a voltage of an effective value applied between row and column electrodes. The apparatus includes an image data buffer memory for storing and outputting a digital image data of one frame, transferred from an external circuit, in the form of an image data matrix; a matrix generator for outputting data having a predetermined orthogonal matrix; a converter for converting the image data with the use of the orthogonal matrix into an converted data matrix and for outputting the converted data matrix; a converted data buffer memory for storing and outputting the converted data matrix; a driver for driving the liquid crystal display in synchronism with a row signal, which applies the orthogonal matrix to the row electrodes of the liquid crystal display, and also a column signal which applies the converted data matrix to the column electrodes of the liquid crystal display.