Patents by Inventor Manadher KHARROUBI

Manadher KHARROUBI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10803223
    Abstract: A system and method for estimating a floorplan designs based on feedback to machine learning algorithms to accumulate data for improving future floorplan design estimates and reducing design time.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: October 13, 2020
    Assignee: ARTERIS, INC.
    Inventor: Manadher Kharroubi
  • Patent number: 10719651
    Abstract: A SoC interconnect network topology is represented. The corresponding SoC floorplan is divided into windows, which are contiguous and non-overlapping. Within each window a subnetwork of the SoC interconnect network topology is defined that includes links or communication paths between IP blocks in the window as well as links or communication paths that traverse the window. At the shared boundaries of the windows, ports are added and defined as virtual ports. The overall SoC topology can be optimized and synthesized by optimizing each window independently and then incrementally optimizing all links, from end-to-end, that traverse two or more windows. The SoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of elements within the floorplan is automatically computed and recommended. Locations can also be edited. Statistical metrics are calculated, including wire length, switch area, SoC area, and maximum signal propagation rate.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: July 21, 2020
    Assignee: ARTERIS, INC.
    Inventors: Raul A. Garibay, Jr., Manadher Kharroubi
  • Publication number: 20190205494
    Abstract: A system and method for estimating a floorplan designs based on feedback to machine learning algorithms to accumulate data for improving future floorplan design estimates and reducing design time.
    Type: Application
    Filed: November 2, 2018
    Publication date: July 4, 2019
    Applicant: Arteris, Inc.
    Inventor: Manadher KHARROUBI
  • Publication number: 20190205493
    Abstract: A SoC interconnect network topology is represented. The corresponding SoC floorplan is divided into windows, which are contiguous and non-overlapping. Within each window a subnetwork of the SoC interconnect network topology is defined that includes links or communication paths between IP blocks in the window as well as links or communication paths that traverse the window. At the shared boundaries of the windows, ports are added and defined as virtual ports. The overall SoC topology can be optimized and synthesized by optimizing each window independently and then incrementally optimizing all links, from end-to-end, that traverse two or more windows. The SoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of elements within the floorplan is automatically computed and recommended. Locations can also be edited. Statistical metrics are calculated, including wire length, switch area, SoC area, and maximum signal propagation rate.
    Type: Application
    Filed: December 30, 2017
    Publication date: July 4, 2019
    Applicant: Arteris, Inc.
    Inventors: Raul A. GARIBAY, Manadher KHARROUBI