Patents by Inventor Manami Kudou

Manami Kudou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pad layout and lead layout in semiconductor device having a center circuit
    Patent number: 6617622
    Abstract: A semiconductor device includes a semiconductor chip and a circuit formed in the semiconductor chip. Pads are arranged in a plurality of rows on the semiconductor chip and electrically connected to the circuit. The pads on adjacent rows are offset from each other. Leads are provided on the semiconductor chip and bonding wires selectively connect the leads to the pads.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: September 9, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Manami Kudou, Masaru Koyanagi
  • Semiconductor memory device
    Patent number: 6510087
    Abstract: A semiconductor memory device comprises a memory cell array, a first latch circuit group, and a second latch circuit group. The first latch circuit group sequentially outputs n/2 bit read data of n-bit read data from the memory cell array in response to sequentially shifted read control signals. The second latch circuit group sequentially outputs the remaining n/2 bit read data in response to the sequentially shifted read control signal.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: January 21, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Manami Kudou, Kazuhide Yoneya, Masaru Koyanagi, Toshiki Hisada, Katsuki Matsudera
  • Semiconductor memory device
    Publication number: 20020036928
    Abstract: A semiconductor memory device comprises a memory cell array, a first latch circuit group, and a second latch circuit group. The first latch circuit group sequentially outputs n/2 bit read data of n-bit read data from the memory cell array in response to sequentially shifted read control signals. The second latch circuit group sequentially outputs the remaining n/2 bit read data in response to the sequentially shifted read control signal.
    Type: Application
    Filed: September 25, 2001
    Publication date: March 28, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Manami Kudou, Kazuhide Yoneya, Masaru Koyanagi, Toshiki Hisada, Katsuki Matsudera
  • Pad layout and lead layout in semiconductor device
    Patent number: 6303948
    Abstract: A semiconductor device includes a semiconductor chip and a circuit formed in the semiconductor chip. Pads are arranged in a plurality of rows on the semiconductor chip and electrically connected to the circuit. The pads on adjacent rows are offset from each other. Leads are provided on the semiconductor chip and bonding wires selectively connect the leads to the pads.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: October 16, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Manami Kudou, Masaru Koyanagi
  • Pad layout and lead layout in semiconductor device
    Publication number: 20010013662
    Abstract: A semiconductor device includes a semiconductor chip and a circuit formed in the semiconductor chip. Pads are arranged in a plurality of rows on the semiconductor chip and electrically connected to the circuit. The pads on adjacent rows are offset from each other. Leads are provided on the semiconductor chip and bonding wires selectively connect the leads to the pads.
    Type: Application
    Filed: April 17, 2001
    Publication date: August 16, 2001
    Inventors: Manami Kudou, Masaru Koyanagi