Abstract: A method of implementing a processor architecture and corresponding system includes operands of a first size and a datapath of a second size. The second size is different from the first size. Given a first array of registers and a second array of registers, each register of the first and second arrays being of the second size, selecting a first register and corresponding second register from the first array and the second array, respectively, to perform operations of the first size. This allows a user, who is interfacing with the hardware processor through software, to provide data of the datapath bit-width instead of the register bit-width. Advantageously, the user is agnostic to the size of the registers.

Abstract: A method of translating a virtual address into a physical memory address in an ARM System Memory Management Unit version 3 (SMMUv3) system includes searching a Configuration Cache memory for a matching tag that matches an associated tag upon receiving the virtual address and the associated tag, and extracting, in a single memory lookup cycle, a matching data field associated with the matching tag when the matching tag is found in the Configuration Cache memory. A matching data field of the Configuration Cache memory includes a matching Stream Table Entry (STE) and a matching Context Descriptor (CD), both associated with the matching tag. The Configuration Cache memory may be configured as a content-addressable memory. The method further includes storing entries associated with a multiple memory lookup cycle virtual address-to-physical address translation into the Configuration Cache memory, each of the entries including a tag, an associated STE and an associated CD.

Abstract: A method of implementing a processor architecture and corresponding system includes operands of a first size and a datapath of a second size. The second size is different from the first size. Given a first array of registers and a second array of registers, each register of the first and second arrays being of the second size, selecting a first register and corresponding second register from the first array and the second array, respectively, to perform operations of the first size. This allows a user, who is interfacing with the hardware processor through software, to provide data of the datapath bit-width instead of the register bit-width. Advantageously, the user is agnostic to the size of the registers.

Abstract: A method of implementing a processor architecture and corresponding system includes operands of a first size and a datapath of a second size. The second size is different from the first size. Given a first array of registers and a second array of registers, each register of the first and second arrays being of the second size, selecting a first register and corresponding second register from the first array and the second array, respectively, to perform operations of the first size. Advantageously, this allows a user, who is interfacing with the hardware processor through software, to provide data to the processor agnostic to the size of the registers and datapath bit-width of the processor.

Abstract: A method of translating a virtual address into a physical memory address in an ARM SMMUv3 system may comprise searching a Configuration Cache memory for a matching tag that matches the associated tag upon receiving the virtual address and an associated tag, and extracting, in a single memory lookup cycle, a matching data field associated with the matching tag when the matching tag is found in the Configuration Cache memory. The matching data field of the Configuration Cache may comprise a matching Stream Table Entry (STE) and a matching Context Descriptor (CD), both associated with the matching tag. The Configuration Cache may be configured as a content-addressable memory. The method may further comprise storing entries associated with a multiple memory lookup cycle virtual address-to-physical address translation into the Configuration Cache memory, each of the entries comprising a tag, an associated STE and an associated CD.

Abstract: In an embodiment, a method includes monitoring a temperature of a semiconductor chip and adjusting a supply voltage to the semiconductor chip based on the monitored temperature. The temperature may be monitored by a temperature sensor located on-chip or off-chip. Adjusting the supply voltage includes increasing the supply voltage as a function of the monitored temperature decreasing. The increase to the supply voltage occurs only if the monitored temperature is below a threshold temperature. The supply voltage adjustment is determined by a linear relationship having a negative slope with temperature.

Abstract: A method of implementing a processor architecture and corresponding system includes operands of a first size and a datapath of a second size. The second size is different from the first size. Given a first array of registers and a second array of registers, each register of the first and second arrays being of the second size, selecting a first register and corresponding second register from the first array and the second array, respectively, to perform operations of the first size. This allows a user, who is interfacing with the hardware processor through software, to provide data of the datapath bit-width instead of the register bit-width. Advantageously, the user is agnostic to the size of the registers.

Abstract: In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element, a first data leg, and a second data leg. The first and second data legs may be coupled to the storage element. Clock selection logic may be coupled to the first and second data legs. The clock selection logic may have a select input for selecting between the first and second data legs. The slave latch may be coupled to the master latch.

Abstract: In an embodiment, a method includes monitoring a temperature of a semiconductor chip and adjusting a supply voltage to the semiconductor chip based on the monitored temperature. The temperature may be monitored by a temperature sensor located on-chip or off-chip. Adjusting the supply voltage includes increasing the supply voltage as a function of the monitored temperature decreasing. The increase to the supply voltage occurs only if the monitored temperature is below a threshold temperature. The supply voltage adjustment is determined by a linear relationship having a negative slope with temperature.

Abstract: In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element, a first data leg, and a second data leg. The first and second data legs may be coupled to the storage element. Clock selection logic may be coupled to the first and second data legs. The clock selection logic may have a select input for selecting between the first and second data legs. The slave latch may be coupled to the master latch.