Abstract: A console and headset system locally trains machine learning models to perform customized online learning tasks. To customize the online learning models for specific users of the system without using outside resources, the system trains the models to compare a target frame to stored calibration frames, rather than directly inferring information about a target frame. During deployment, an embedding is generated for the target frame. A sample embedding that is closest to the target embedding is selected from a group of embeddings of calibration frames. The information about the selected embedding and target embedding and ground truths for the calibration frame are provided as inputs to one of the trained models. The model predicts a difference between the target frame and the calibration frame, which can be used to determine information about the target frame.

Abstract: Examples of image sensors are described herein. In an example, an image sensor may comprise an array of hybrid pixels, where each hybrid pixel includes light sensing unit and a non-volatile memory component coupled to the light sensing unit. The light sensing unit comprises a light detecting element and a charge to voltage conversion unit. The charge to voltage conversion unit is to provide an output pixel signal (VPD), based on photo-electrons generated by the light detecting element. Further, the non-volatile component when calibrated to an initial resistance state is to compress the output pixel signal (VPD) during exposure.

Abstract: Examples of image sensors are described herein. In an example, an image sensor may comprise an array of hybrid pixels, where each hybrid pixel includes light sensing unit and a non-volatile memory component coupled to the light sensing unit. The light sensing unit comprises a light detecting element and a charge to voltage conversion unit. The charge to voltage conversion unit is to provide an output pixel signal (VPD), based on photo-electrons generated by the light detecting element. Further, the non-volatile component when calibrated to an initial resistance state is to compress the output pixel signal (VPD) during exposure.

Abstract: A circuit for implementing an artificial neuron comprises: an integrator for an input signal to produce a voltage signal; a signal generator linked to the integrator output producing two output signals when the voltage is at or above a predetermined voltage, a first signal for an output pulse of the neuron and a second signal for a control pulse; a resistive memory comprising two terminals switching from a high to low resistance state in a time following a statistical distribution specific to the memory, a first terminal linked to the output of the integrator; a transistor linked to a branch at zero potential to a second terminal of the resistive memory, controlled by the second output signal such that in the presence of a pulse of voltage the resistive memory switches from its high resistance state to its low resistance state with a view to lowering the voltage.

Abstract: A device for transporting two or more articles to two or more locations comprising: one or more holding units for carrying the two or more articles one or more orifices for loading and/or delivering the articles a controlling unit for directing the movement and operations of the device a flying attachment for transporting the device through air

Abstract: A neural network comprises a plurality of artificial neurons and a plurality of artificial synapses each input neuron being connected to each output neuron by way of an artificial synapse, the network being characterized in that each synapse consists of a first memristive device connected to a first input of an output neuron and of a second memristive device, mounted in opposition to said first device and connected to a second, complemented, input of said output neuron so that said output neuron integrates the difference between the currents originating from the first and second devices.

Abstract: A neuromorphic system comprises a set of at least one input neuron, a set of at least one output neuron and a synaptic network formed from a set of at least one variable-resistance memristive component, said synaptic network connecting at least one input neuron to at least one output neuron, the resistance of the at least one memristive component being adjusted by delivering to the synaptic network write pulses generated by the at least one input neuron, and return pulses generated by the at least one output neuron, the characteristics of the write and return pulses being deduced from the intrinsic characteristics of the at least one memristive component so that the combination of a write pulse and a return pulse in the at least one memristive component results in a modification of its resistance according to a learning rule chosen beforehand.

Abstract: A delay generator comprises at least one programmable resistor RPCM made of a chalcogenide-based phase-change material, said resistor RPCM being initialized, so as to generate a delay, in a way such that the resistance of the resistor RPCM equals a pre-set initial value R0 and such that the chalcogenide is in the amorphous phase, and a comparator comparing a reference electrical quantity that is stable over time with a variable electrical quantity representative of the resistance of the programmable resistor RPCM, the comparator generating a singularity signal s, said singularity being generated when the difference between the two electrical quantities changes sign.

Abstract: A circuit for implementing an artificial neuron comprises: an integrator for an input signal to produce a voltage signal; a signal generator linked to the integrator output producing two output signals when the voltage is at or above a predetermined voltage, a first signal for an output pulse of the neuron and a second signal for a control pulse; a resistive memory comprising two terminals switching from a high to low resistance state in a time following a statistical distribution specific to the memory, a first terminal linked to the output of the integrator; a transistor linked to a branch at zero potential to a second terminal of the resistive memory, controlled by the second output signal such that in the presence of a pulse of voltage the resistive memory switches from its high resistance state to its low resistance state with a view to lowering the voltage.

Abstract: A neuromorphic system comprises a set of at least one input neuron, a set of at least one output neuron and a synaptic network formed from a set of at least one variable-resistance memristive component, said synaptic network connecting at least one input neuron to at least one output neuron, the resistance of the at least one memristive component being adjusted by delivering to the synaptic network write pulses generated by the at least one input neuron, and return pulses generated by the at least one output neuron, the characteristics of the write and return pulses being deduced from the intrinsic characteristics of the at least one memristive component so that the combination of a write pulse and a return pulse in the at least one memristive component results in a modification of its resistance according to a learning rule chosen beforehand.

Abstract: A neural network comprises a plurality of artificial neurons and a plurality of artificial synapses each input neuron being connected to each output neuron by way of an artificial synapse, the network being characterized in that each synapse consists of a first memristive device connected to a first input of an output neuron and of a second memristive device, mounted in opposition to said first device and connected to a second, complemented, input of said output neuron so that said output neuron integrates the difference between the currents originating from the first and second devices.

Abstract: A delay generator comprises at least one programmable resistor RPCM made of a chalcogenide-based phase-change material, said resistor RPCM being initialized, so as to generate a delay, in a way such that the resistance of the resistor RPCM equals a pre-set initial value R0 and such that the chalcogenide is in the amorphous phase, and a comparator comparing a reference electrical quantity that is stable over time with a variable electrical quantity representative of the resistance of the programmable resistor RPCM, the comparator generating a singularity signal s, said singularity being generated when the difference between the two electrical quantities changes sign.