Abstract: A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.

Abstract: A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.

Abstract: A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to the program voltage target; a sensor circuit that compares a duty cycle of the control signal to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.

Abstract: A voltage generation system might include a selectively-enabled resistive voltage divider having a first resistor connected between an output of the voltage generation system and a first feedback node and having a second resistor connected between the first feedback node and a first voltage node; a selectively-enabled capacitive voltage divider having a first capacitor connected between the output and a second feedback node and having a second capacitor connected between the second feedback node and the first voltage node; a comparator having a first input connected to the second feedback node, having a second input connected to a control signal node, and having an output; and a voltage generation circuit configured to generate a voltage level at the output responsive to a logic level of the output of the comparator and to a clock signal; wherein the first feedback node is selectively connected to the second feedback node.

Abstract: A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to the program voltage target; a sensor circuit that compares a duty cycle of the control signal to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.

Abstract: A voltage generation system might include a selectively-enabled resistive voltage divider having a first resistor connected between an output of the voltage generation system and a first feedback node and having a second resistor connected between the first feedback node and a first voltage node; a selectively-enabled capacitive voltage divider having a first capacitor connected between the output and a second feedback node and having a second capacitor connected between the second feedback node and the first voltage node; a comparator having a first input connected to the second feedback node, having a second input connected to a control signal node, and having an output; and a voltage generation circuit configured to generate a voltage level at the output responsive to a logic level of the output of the comparator and to a clock signal; wherein the first feedback node is selectively connected to the second feedback node.

Abstract: A voltage generation system might include a resistive voltage divider having a first resistance connected between its output and a first feedback node and a second resistance connected between the first feedback node and a first voltage node, a capacitive voltage divider having a first capacitance connected between its output and a second feedback node and a second capacitance connected between the second feedback node and the first voltage node, a comparator having an input connected to the second feedback node, and a voltage generation circuit configured to generate a voltage level at its output responsive to an output of the comparator and to a clock signal, wherein the first feedback node is selectively connected to the second feedback node and selectively connected to a second voltage node, wherein the first resistance is selectively connected to the first feedback node, and wherein the second resistance is selectively connected to the first voltage node.