Patents by Inventor Manar EL-CHAMMAS

Manar EL-CHAMMAS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230359571
    Abstract: Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.
    Type: Application
    Filed: June 30, 2023
    Publication date: November 9, 2023
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Patent number: 11726925
    Abstract: Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: August 15, 2023
    Assignee: Mythic, Inc.
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Patent number: 11626884
    Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: April 11, 2023
    Assignee: Mythic, Inc.
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Publication number: 20220414025
    Abstract: Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.
    Type: Application
    Filed: August 31, 2022
    Publication date: December 29, 2022
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Patent number: 11467984
    Abstract: Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: October 11, 2022
    Assignee: Mythic, Inc.
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Publication number: 20220173747
    Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.
    Type: Application
    Filed: February 18, 2022
    Publication date: June 2, 2022
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Patent number: 11296717
    Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: April 5, 2022
    Assignee: Mythic, Inc.
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Publication number: 20210143832
    Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 13, 2021
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Patent number: 10903844
    Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: January 26, 2021
    Assignee: Mythic, Inc.
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Publication number: 20200083897
    Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Patent number: 10523230
    Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: December 31, 2019
    Assignee: Mythic, Inc.
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Publication number: 20190326921
    Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Patent number: 10389375
    Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: August 20, 2019
    Assignee: Mythic, Inc.
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Publication number: 20190179776
    Abstract: Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.
    Type: Application
    Filed: February 20, 2019
    Publication date: June 13, 2019
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Patent number: 10255205
    Abstract: Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: April 9, 2019
    Assignee: Mythic, Inc.
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Patent number: 10255551
    Abstract: An integrated circuit and method are provided for performing weighted sum computations. The circuit includes: a plurality of current generators interconnected and arranged into pairs, a positive summation node, a negative summation node, and an input generation circuit. For each pair of current generators, the control terminal of each element is electrically connected to an input node. One of the current generators has its drain connected to the positive summation node while the other current generation element has its drain connected to the negative summation node. The remaining terminals on both current generators are connected to a reference, which may be shared. Each pair of current generator source predetermined amounts of current onto the two summation nodes when the following conditions occur: the input node is at an activation voltage, and the two summation nodes are at a predetermined target voltage.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: April 9, 2019
    Assignees: The Regents of The University of Michigan, Mythic, Inc.
    Inventors: David Alan Fick, Laura E. Fick, Skylar J. Skrzyniarz, Manar El-Chammas
  • Publication number: 20190087356
    Abstract: Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 21, 2019
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Publication number: 20180247192
    Abstract: An integrated circuit and method are provided for performing weighted sum computations. The circuit includes: a plurality of current generators interconnected and arranged into pairs, a positive summation node, a negative summation node, and an input generation circuit. For each pair of current generators, the control terminal of each element is electrically connected to an input node. One of the current generators has its drain connected to the positive summation node while the other current generation element has its drain connected to the negative summation node. The remaining terminals on both current generators are connected to a reference, which may be shared. Each pair of current generator source predetermined amounts of current onto the two summation nodes when the following conditions occur: the input node is at an activation voltage, and the two summation nodes are at a predetermined target voltage.
    Type: Application
    Filed: February 7, 2018
    Publication date: August 30, 2018
    Inventors: David Alan FICK, Laura E. FICK, Skylar J. SKRZYNIARZ, Manar EL-CHAMMAS
  • Patent number: 9503119
    Abstract: A switched current pipeline analog-to-digital converter (ADC) integrated circuit. The integrated circuit comprises a track and hold circuit (T/H) and a residue amplifier. The T/H is configured to generate a differential output of the T/H based on an analog input. The residue amplifier is coupled to the T/H, configured to capture a sample of a common mode signal of the differential output of the T/H during a periodic pulse interval, wherein the pulse interval is less than half of the time duration of the period of the pulse, configured to generate a corrected input common mode feedback signal based in part on the sample of the common mode signal of the differential output of the T/H, and configured to generate a differential output of the residue amplifier based on the differential output of the T/H and based on the corrected input common mode feedback signal.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: November 22, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jesse Coulon, Manar El-Chammas, Xiaopeng Li, Shigenobu Kimura
  • Publication number: 20150349795
    Abstract: A switched current pipeline analog-to-digital converter (ADC) integrated circuit. The integrated circuit comprises a track and hold circuit (T/H) and a residue amplifier. The T/H is configured to generate a differential output of the T/H based on an analog input. The residue amplifier is coupled to the T/H, configured to capture a sample of a common mode signal of the differential output of the T/H during a periodic pulse interval, wherein the pulse interval is less than half of the time duration of the period of the pulse, configured to generate a corrected input common mode feedback signal based in part on the sample of the common mode signal of the differential output of the T/H, and configured to generate a differential output of the residue amplifier based on the differential output of the T/H and based on the corrected input common mode feedback signal.
    Type: Application
    Filed: May 18, 2015
    Publication date: December 3, 2015
    Inventors: Jesse COULON, Manar EL-CHAMMAS, Xiaopeng LI, Shigenobu KIMURA