Abstract: A method, apparatus and product for hard error simulation and usage thereof. The method comprises obtaining a design of a circuit, which comprises one or more monitoring signals for identifying errors and one or more critical nodes; obtaining a trace of a run of a test of the circuit; and obtaining a hard error fault on a node. The method comprises determining a hard-error test coverage for the hard error fault, wherein the hard-error test coverage is indicative of whether or not the one or more monitoring signals identifies the hard error fault during an execution of the test, and wherein said determining comprises: simulating the execution of the circuit together with the hard error fault and noting whether or not any one or more of the one or more monitoring signals has detected the hard error fault. An indication of the hard-error test coverage may be outputted.

Abstract: A method, apparatus and product for hard error simulation and usage thereof. The method comprises obtaining a design of a circuit, which comprises one or more monitoring signals for identifying errors and one or more critical nodes; obtaining a trace of a run of a test of the circuit; and obtaining a hard error fault on a node. The method comprises determining a hard-error test coverage for the hard error fault, wherein the hard-error test coverage is indicative of whether or not the one or more monitoring signals identifies the hard error fault during an execution of the test, and wherein said determining comprises: simulating the execution of the circuit together with the hard error fault and noting whether or not any one or more of the one or more monitoring signals has detected the hard error fault. An indication of the hard-error test coverage may be outputted.