Patents by Inventor Manar Ibrahim El-Chammas
Manar Ibrahim El-Chammas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10037814Abstract: A track and hold circuit includes a primary sampling capacitor, a primary switching transistor, and a cancellation transistor. The primary switching transistor is configured to provide a track state that connects an input signal to the primary sampling capacitor and a hold state that isolates the input signal from the primary sampling capacitor. The cancellation transistor is coupled to the primary sampling capacitor. The cancellation transistor is configured to inject a charge onto the primary sampling capacitor that cancels a charge injected onto the primary sampling capacitor by the primary switching transistor while the primary switching transistor is in the hold state.Type: GrantFiled: September 9, 2016Date of Patent: July 31, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Himanshu Aggrawal, Manar Ibrahim El-Chammas
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Patent number: 9941896Abstract: An analog-to-digital converter (ADC) may include a comparator and a metastability detector. The comparator may be configured to compare an input signal to a reference signal to determine whether the input signal exceeds the reference signal. The comparator may also be configured to output a comparator output based on the determination. An ADC output may be based at least in part on the comparator output. The metastability detector may be coupled to the comparator and may be configured to determine, based at least in part on the comparator output, that the comparator is operating under metastable conditions and may output a metastability detector output.Type: GrantFiled: October 14, 2016Date of Patent: April 10, 2018Assignee: Texas Instruments IncorporatedInventor: Manar Ibrahim El-Chammas
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Patent number: 9831886Abstract: A system and method where a comparator is operatively coupled to an output of a Digital-to-analog Converter (DAC). The DAC may comprise a single DAC core or a plurality of interleaved DAC cores. The comparator is configured to capture properties of DAC core output. A digital engine is operatively coupled to receive output of the comparator and configured to calculate a cross-correlation between comparator output and input to the DAC core(s). The digital engine may be configured to determine if the skew of each DAC core is positive or negative and to determine if a skew correction term for the DAC core(s) should be decreased or increased, based on the skew of each DAC core being positive or negative, respectively. In interleaved DAC core devices, clock frequency sampling edges of the comparator may alternate between clock edges of each of the interleaved DAC cores.Type: GrantFiled: December 22, 2015Date of Patent: November 28, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Manar Ibrahim El-Chammas
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Publication number: 20170111055Abstract: An analog-to-digital converter (ADC) may include a comparator and a metastability detector. The comparator may be configured to compare an input signal to a reference signal to determine whether the input signal exceeds the reference signal. The comparator may also be configured to output a comparator output based on the determination. An ADC output may be based at least in part on the comparator output. The metastability detector may be coupled to the comparator and may be configured to determine, based at least in part on the comparator output, that the comparator is operating under metastable conditions and may output a metastability detector output.Type: ApplicationFiled: October 14, 2016Publication date: April 20, 2017Inventor: Manar Ibrahim EL-CHAMMAS
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Publication number: 20170076823Abstract: A track and hold circuit includes a primary sampling capacitor, a primary switching transistor, and a cancellation transistor. The primary switching transistor is configured to provide a track state that connects an input signal to the primary sampling capacitor and a hold state that isolates the input signal from the primary sampling capacitor. The cancellation transistor is coupled to the primary sampling capacitor. The cancellation transistor is configured to inject a charge onto the primary sampling capacitor that cancels a charge injected onto the primary sampling capacitor by the primary switching transistor while the primary switching transistor is in the hold state.Type: ApplicationFiled: September 9, 2016Publication date: March 16, 2017Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Himanshu AGGRAWAL, Manar Ibrahim EL-CHAMMAS
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Publication number: 20160182076Abstract: A system and method where a comparator is operatively coupled to an output of a Digital-to-analog Converter (DAC). The DAC may comprise a single DAC core or a plurality of interleaved DAC cores. The comparator is configured to capture properties of DAC core output. A digital engine is operatively coupled to receive output of the comparator and configured to calculate a cross-correlation between comparator output and input to the DAC core(s). The digital engine may be configured to determine if the skew of each DAC core is positive or negative and to determine if a skew correction term for the DAC core(s) should be decreased or increased, based on the skew of each DAC core being positive or negative, respectively. In interleaved DAC core devices, clock frequency sampling edges of the comparator may alternate between clock edges of each of the interleaved DAC cores.Type: ApplicationFiled: December 22, 2015Publication date: June 23, 2016Applicant: Texas Instruments IncorporatedInventor: Manar Ibrahim El-Chammas
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Patent number: 9136856Abstract: A circuit includes a track and hold (T/H) block to track an analog input signal during a track phase and to hold the analog input signal during a hold phase. A pipelined converter stage includes an analog to digital converter (ADC) receives the analog input signal from the T/H block and generates a digital output signal corresponding to the analog input signal. A digital to analog converter (DAC) element in the pipelined converter stage receives the digital output signal from the ADC and generates a current output signal representing an analog value for a portion of the analog input signal. A detector monitors the current output signal of the DAC element with respect to a predetermined reference current during the track phase and generates a trim signal if the current output signal is different from the predetermined reference current.Type: GrantFiled: February 26, 2014Date of Patent: September 15, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Manar Ibrahim El-Chammas
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Publication number: 20150244386Abstract: A circuit includes a track and hold (T/H) block to track an analog input signal during a track phase and to hold the analog input signal during a hold phase. A pipelined converter stage includes an analog to digital converter (ADC) receives the analog input signal from the T/H block and generates a digital output signal corresponding to the analog input signal. A digital to analog converter (DAC) element in the pipelined converter stage receives the digital output signal from the ADC and generates a current output signal representing an analog value for a portion of the analog input signal. A detector monitors the current output signal of the DAC element with respect to a predetermined reference current during the track phase and generates a trim signal if the current output signal is different from the predetermined reference current.Type: ApplicationFiled: February 26, 2014Publication date: August 27, 2015Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: MANAR IBRAHIM EL-CHAMMAS
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Patent number: 8547269Abstract: An apparatus comprises: a coarse voltage level comparator that generates a coarse voltage level comparison; a folder, a fine analog to digital (ADC) comparator coupled to an output of the folder, wherein an output of the fine ADC is cyclical; an up encoder coupled to an output of the fine ADC encoder, the up encoder configured to output a first value if the cyclical output of the fine ADC is in a defined downward transition; and a fold information generator coupled to an output of the up encoder, wherein the fold information generator is configured to generate a determination as to in which fold an analog voltage occurs.Type: GrantFiled: March 14, 2012Date of Patent: October 1, 2013Assignee: Texas Instruments IncorporatedInventor: Manar Ibrahim El-Chammas
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Publication number: 20130194120Abstract: An apparatus comprises: a coarse voltage level comparator that generates a coarse voltage level comparison; a folder, a fine analog to digital (ADC) comparator coupled to an output of the folder, wherein an output of the fine ADC is cyclical; an up encoder coupled to an output of the fine ADC encoder, the up encoder configured to output a first value if the cyclical output of the fine ADC is in a defined downward transition; and a fold information generator coupled to an output of the up encoder, wherein the fold information generator is configured to generate a determination as to in which fold an analog voltage occurs.Type: ApplicationFiled: March 14, 2012Publication date: August 1, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Manar Ibrahim El-Chammas