Patents by Inventor Manas Behera

Manas Behera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10165531
    Abstract: In a wireless sensor actuator network, a time slot for transmission of a signal to a first device and a second device of the wireless sensor actuator network may be determined. During the time slot, the signal may be transmitted via a first frequency channel and first antenna to the first device and via a second frequency channel and second antenna to the second device in parallel. The first frequency channel may be different from the second frequency channel. Further, the first frequency channel and the second frequency channel may be selected based on a power level to transmit the signal to the first device, a power level to transmit the signal to the second device, an angle to transmit the signal to the first device, and an angle to transmit the signal to the second device.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 25, 2018
    Assignee: Spearlx Technologies, Inc.
    Inventor: Manas Behera
  • Patent number: 10143029
    Abstract: A wireless communication device is described in one example comprising a first communication module circuitry to communicatively couple the wireless communication device with a first network, the first communication module circuitry to receive a reject message from the first network to disable communications with the first network, a processor to store, in memory, information corresponding to the communications with the first network; and a second communication module circuitry to communicatively couple the wireless communication device with a second network, the second communication module circuitry to send the information to a remote service monitor, wherein the first communication module circuitry includes a first Subscriber Identity Module (SIM) or a first virtual SIM and the second communication module circuitry includes a second SIM or a second virtual SIM. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: November 27, 2018
    Assignee: Intel IP Corporation
    Inventors: Manas Behera, Anuj Sethi
  • Publication number: 20170353939
    Abstract: A wireless communication device is described in one example comprising a first communication module circuitry to communicatively couple the wireless communication device with a first network, the first communication module circuitry to receive a reject message from the first network to disable communications with the first network, a processor to store, in memory, information corresponding to the communications with the first network; and a second communication module circuitry to communicatively couple the wireless communication device with a second network, the second communication module circuitry to send the information to a remote service monitor, wherein the first communication module circuitry includes a first Subscriber Identity Module (SIM) or a first virtual SIM and the second communication module circuitry includes a second SIM or a second virtual SIM. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: May 2, 2017
    Publication date: December 7, 2017
    Inventors: Manas Behera, Anuj Sethi
  • Publication number: 20170332287
    Abstract: A radio communication device may include a measurement circuit configured to perform radio measurement to identify one or more cells of a combined CS-PS network in anticipation of circuit-switched orders, and a control circuit configured to identify a pending circuit-switched order supported by the combined CS-PS network while attached to a current network, and switch from the current network to the combined CS-PS network to engage in the pending circuit-switched using a selected cell of the one or more cells.
    Type: Application
    Filed: April 6, 2017
    Publication date: November 16, 2017
    Inventors: Anuj Sethi, Manas Behera
  • Patent number: 8963613
    Abstract: A current mirror circuit is described. The current mirror circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are coupled at a bias voltage. The current mirror circuit also includes an auxiliary transistor that is biased into weak inversion by receiving the bias voltage at a gate of the auxiliary transistor after being reduced by an offset voltage. The sources of the first transistor, second transistor and auxiliary transistor are coupled together. A primary current from the drain of the second transistor is combined with an auxiliary current from the drain of the auxiliary transistor to produce an output current.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: February 24, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Manas Behera, Yanping Ding, Junxiong Deng
  • Patent number: 8952742
    Abstract: New devices and methods capable of detecting a true Root-Mean-Square (RMS) power level of an analog input signal are disclosed. For example, an electronic circuit can include a squaring circuit that receives the analog input signal and processes the analog input signal so as to produce a squared-output of the analog input signal using an analog transfer function of the squaring circuit, and a square-root circuit that receives the squared-output and processes the squared-output using an analog transfer function of the square-root circuit so as to produce an analog RMS output signal representing the true RMS power level of the analog input signal.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: February 10, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Chandra B. Prakash, Manas Behera, Gregory T. Uehara
  • Publication number: 20140118050
    Abstract: New devices and methods capable of detecting a true Root-Mean-Square (RMS) power level of an analog input signal are disclosed. For example, an electronic circuit can include a squaring circuit that receives the analog input signal and processes the analog input signal so as to produce a squared-output of the analog input signal using an analog transfer function of the squaring circuit, and a square-root circuit that receives the squared-output and processes the squared-output using an analog transfer function of the square-root circuit so as to produce an analog RMS output signal representing the true RMS power level of the analog input signal.
    Type: Application
    Filed: October 30, 2013
    Publication date: May 1, 2014
    Applicant: Marvell World Trade Ltd.
    Inventors: Chandra B. PRAKASH, Manas Behera, Gregory T. Uehara
  • Patent number: 8589750
    Abstract: A built-in self test (BiST) system is described. The BiST system includes a circuit-under-test. The BiST system also includes one or more embedded sensors. Each of the embedded sensors includes one or more switches connected to one or more nodes within the circuit-under-test. The BiST system further includes a signal generator. The BiST system also includes a bus interface. The bus interface provides for external access of the BiST system.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: November 19, 2013
    Assignee: QUALCOMM, Incorporated
    Inventors: Gaurab Banerjee, Manas Behera, Kenneth Charles Barnett
  • Patent number: 8422975
    Abstract: Disclosed are circuits, techniques and methods for removing one or more harmonics from a waveform that has been mixed with a local oscillator. In one particular example, such a waveform may also be mixed with a second local oscillator at a different frequency and combined with the first mixed waveform to suppress and/or substantially remove the one or more harmonics.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: April 16, 2013
    Assignee: QUALCOMM, Incorporated
    Inventors: Manas Behera, Junxiong Deng
  • Publication number: 20130038384
    Abstract: A current mirror circuit is described. The current mirror circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are coupled at a bias voltage. The current mirror circuit also includes an auxiliary transistor that is biased into weak inversion by receiving the bias voltage at a gate of the auxiliary transistor after being reduced by an offset voltage. The sources of the first transistor, second transistor and auxiliary transistor are coupled together. A primary current from the drain of the second transistor is combined with an auxiliary current from the drain of the auxiliary transistor to produce an output current.
    Type: Application
    Filed: July 17, 2012
    Publication date: February 14, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Manas Behera, Yanping Ding, Junxiong Deng
  • Patent number: 8310309
    Abstract: A differential Low Noise Amplifier (LNA) includes a first stage of resistive feedback amplifiers and second stage of complementary amplifiers, where the outputs of the first stage are coupled to the inputs of the second stage in a cross-coupled fashion. An inductive load, such as a transformer, combines signals output from the complementary amplifiers of the second stage. In one example, the LNA has an input impedance of less than 75 ohms, a noise factor of less than 2 dB, and a gain of more than 20 dB. Due to the low input impedance, the LNA is usable to amplify a signal received from a source having a similar low impedance without the use of an impedance matching network between the output of the source and the input of the LNA.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: November 13, 2012
    Assignee: QUALCOMM, Incorporated
    Inventors: Manas Behera, Harish S Muthali, Kenneth Charles Barnett
  • Publication number: 20120017131
    Abstract: A built-in self test (BiST) system is described. The BiST system includes a circuit-under-test. The BiST system also includes one or more embedded sensors. Each of the embedded sensors includes one or more switches connected to one or more nodes within the circuit-under-test. The BiST system further includes a signal generator. The BiST system also includes a bus interface. The bus interface provides for external access of the BiST system.
    Type: Application
    Filed: July 14, 2010
    Publication date: January 19, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventors: Gaurab Banerjee, Manas Behera, Kenneth Charles Barnett
  • Publication number: 20110306300
    Abstract: Disclosed are circuits, techniques and methods for removing one or more harmonics from a waveform that has been mixed with a local oscillator. In one particular example, such a waveform may also be mixed with a second local oscillator at a different frequency and combined with the first mixed waveform to suppress and/or substantially remove the one or more harmonics.
    Type: Application
    Filed: June 9, 2010
    Publication date: December 15, 2011
    Applicant: QUALCOMM INCORPORATED
    Inventors: Manas Behera, Junxiong Deng
  • Publication number: 20110273197
    Abstract: An integrated circuit with Built-in Self Test (BiST) is described. The integrated circuit includes a signal generator used to perform a BiST on the integrated circuit. The integrated circuit also includes a local oscillator used by the signal generator to generate one or more test signals used to perform the BiST on the integrated circuit.
    Type: Application
    Filed: May 7, 2010
    Publication date: November 10, 2011
    Applicant: QUALCOMM INCORPORATED
    Inventors: Gaurab Banerjee, Manas Behera
  • Publication number: 20110267144
    Abstract: A differential Low Noise Amplifier (LNA) includes a first stage of resistive feedback amplifiers and second stage of complementary amplifiers, where the outputs of the first stage are coupled to the inputs of the second stage in a cross-coupled fashion. An inductive load, such as a transformer, combines signals output from the complementary amplifiers of the second stage. In one example, the LNA has an input impedance of less than 75 ohms, a noise factor of less than 2 dB, and a gain of more than 20 dB. Due to the low input impedance, the LNA is usable to amplify a signal received from a source having a similar low impedance without the use of an impedance matching network between the output of the source and the input of the LNA.
    Type: Application
    Filed: May 3, 2010
    Publication date: November 3, 2011
    Applicant: QUALCOMM INCORPORATED
    Inventors: Manas Behera, Harish S. Muthali, Kenneth Charles Barnett
  • Publication number: 20050198216
    Abstract: A method for managing a network includes selecting a first database containing a topology of the network, as an active database that is accessible, selecting a second database as a working database for receiving topology updates, discovering a topology of the network and updating the second database with the discovered topology, and selecting the second database as the active database. Another method includes discovering the network, updating a topology representation of the network in a working database based on the discovering, simultaneous with the discovering and the updating providing access to a topology representation of the network in an active database, and exchanging connections of the working and active databases.
    Type: Application
    Filed: February 2, 2004
    Publication date: September 8, 2005
    Inventors: Manas Behera, Yong Ho