Patents by Inventor Manas Lahon

Manas Lahon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10545866
    Abstract: Disclosed is an improved approach to implement training for memory technologies, where a data valid window is re-determined using boundary information for a new data valid window. The information obtained for the new location of the first edge is used to minimize the computational resources required to identify the location of the second edge. This greatly improves the efficiency of the process to perform the re-training.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 28, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yoshiharu Kato, Manas Lahon, Sandeep Brahmadathan
  • Patent number: 8812898
    Abstract: A system and method are provided for ensuring reliable data transfers by automatically recovering from un-correctable errors detected in data traversing throughout a system and being retrieved from an unreliable intermediate data buffer between a first memory and a secondary slower memory. Additionally, measures to compensate for the use of unreliable or error-prone components and interconnects, such as, for example, SRAM memory as a temporary buffer are provided. Further, measures to detect and correct errors—whatever the type—injected or occurring at any stage throughout traversal of the system are provided.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 19, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manas Lahon, Sandeep Brahmadathan