Abstract: Subsystems and methods disclosed herein provide a reference signal to a power amplifier (PA) of an RF transmitter or transceiver. PTAT and CTAT signals and a temperature indication signal are produced. Based on the temperature indication signal, one of the PTAT or CTAT signals is selected to be used to produce one or more DAC reference signals. Using the selected one of the PTAT or CTAT signals, the one or more DAC reference signals are produced and used to bias the DAC. A multi-bit digital input signal is converted to an analog output signal using the DAC that is biased using the one or more DAC reference signals (produced using the selected one of the PTAT or CTAT signals). Further, the analog signal output by the DAC, or an amplified version thereof, is used as the reference signal that is provided to the PA of the RF transmitter or transceiver.

Abstract: Subsystems and methods disclosed herein provide a reference signal to a power amplifier (PA) of an RF transmitter or transceiver. PTAT and CTAT signals and a temperature indication signal are produced. Based on the temperature indication signal, one of the PTAT or CTAT signals is selected to be used to produce one or more DAC reference signals. Using the selected one of the PTAT or CTAT signals, the one or more DAC reference signals are produced and used to bias the DAC. A multi-bit digital input signal is converted to an analog output signal using the DAC that is biased using the one or more DAC reference signals (produced using the selected one of the PTAT or CTAT signals). Further, the analog signal output by the DAC, or an amplified version thereof, is used as the reference signal that is provided to the PA of the RF transmitter or transceiver.

Abstract: Disclosed embodiments include a direct current to direct current (DC-DC) converter including one or more charge pumps and configured to receive an input voltage and a first clock signal and a second clock signal. The first clock signal and second clock signal may be non-overlapping, and each may alternate between a ground voltage and a first voltage. The DC-DC converter may be configured to produce an output voltage over the clock cycle that has a negative polarity with a magnitude substantially equal to a sum of magnitudes of the input voltage and an integer multiple of the first voltage, the integer multiple being equal to a number of the one or more charge pumps in the DC-DC converter.

Abstract: Disclosed embodiments include a direct current to direct current (DC-DC) converter including one or more charge pumps and configured to receive an input voltage and a first clock signal and a second clock signal. The first clock signal and second clock signal may be non-overlapping, and each may alternate between a ground voltage and a first voltage. The DC-DC converter may be configured to produce an output voltage over the clock cycle that has a negative polarity with a magnitude substantially equal to a sum of magnitudes of the input voltage and an integer multiple of the first voltage, the integer multiple being equal to a number of the one or more charge pumps in the DC-DC converter.

Abstract: A digital DC offset correction circuit (68) provides DC offset correction within a receiver (50) using an area-optimum, rapid acquisition cellular multi-protocol digital dc offset correction scheme. The digital DC offset correction circuit (68) includes an integrator (90), a low pass filter (92), a decimator (94), a digital to analog converter codeword clamp (96), and a digital to analog converter (98).

Abstract: A digital demodulator (100) includes a differentiate and cross multiply stage (102) and a plurality of filter/decimator stages (106, 112, 118 and 108, 114, 120 and 110, 116, 122) that accept both multiple baud rates and multiple modulation deviation frequencies, and that provide a common frequency data stream at their respective outputs. One of said filter/decimator stages is coupled to a primary filter (124) which is followed by a box filter (134). The box filter (134) improves the overall filter response and provides notches at a specified frequency (e.g., 4800 Hz) and its harmonics. Demodulator (100) provides improved sensitivity without the need for any circuit trimming. The filter stages (e.g., 106, 112, 118; 108, 114, 120; and 110, 116, 122) used in demodulator (100) have been optimized to eliminate the need for costly multipliers.

Abstract: A ring inhibiting charging and discharging circuit (100) for use with an amplification circuit (102) that drives a load (108) is responsive to an input (104) and is capable of generating an output (106) corresponding to the input (104). The ring inhibiting charging and discharging circuit (100) includes a charge element (120) that is responsive to the output (112) from the amplification circuit (102). The charge element (120) is capable of charging the load when the input voltage is greater than a preselected multiple of the output voltage. A discharge circuit (130) is responsive to the output (106) from the amplification circuit (102) and includes a feedback circuit (132) and a staging circuit (134). The feedback circuit (132) asserts a difference signal when the output voltage is less than the preselected multiple of the input voltage.

Abstract: A voltage comparator (10) includes a differential amplifier (12), a switched latch (32), and a switch (26). The voltage comparator (10) receives a first input signal (18) and a second input signal (20), and produces a first output (38) and a second output (40) by comparing the first and second input signals. A reset input (30) disables and enables the voltage comparator (10).

Abstract: A decoder circuit (21) and method for providing an amplitude compensated signal by removing the undesired effect of amplitude modulation on a phase modulated signal. The decoder method is provided by demodulating a received inphase receive signal component (10) and quadrature receive signal component (12) of the phase modulated signal and outputting an amplitude varying signal (15) to a feedforward automatic gain control circuit that outputs an amplitude compensated signal (38). The feedforward automatic gain control circuit comprises a detector circuit (16), an offset bias circuit (32), a differencer circuit (30) and a gain control circuit (28).The detector circuit (16) outputs a DC signal (17) representing an amplitude of the inphase receive signal (10) and the quadrature receive signal (12). The offset bias circuit (32) provides a constant current bias (29) to the DC signal (17) thus creating a control signal 31.

Abstract: A wide dynamic range Operational Transconductance Amplifier (OTA) (100) includes a differential voltage to current converter (206) for converting an input voltage to a current level. A pair of programmable folded cascodes (201) are coupled to the output of the converter (206) in order to render the amplifier (100) programmable. Current sources (222 and 226) are employed to provide output sourcing current. There is also included a common mode feedback (106) for maintaining the output signal substantially and equally centered between rails of the operating voltage (208).