Patents by Inventor Mandana Tadayoni
Mandana Tadayoni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9793279Abstract: A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. A conductive word line gate is disposed over a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The thickness of insulation separating the word line gate from the second portion of the channel region is less than that of insulation separating the floating gate from the erase gate.Type: GrantFiled: June 14, 2016Date of Patent: October 17, 2017Assignee: Silicon Storage Technology, Inc.Inventors: Jeng-Wei Yang, Man-Tang Wu, Chun-Ming Chen, Mandana Tadayoni, Chien-Sheng Su, Nhan Do
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Patent number: 9634020Abstract: A method of forming a semiconductor device with memory cells and logic devices on the same silicon-on-insulator substrate. The method includes providing a substrate that includes silicon, a first insulation layer directly over the silicon, and a silicon layer directly over the first insulation layer. Silicon is epitaxially grown on the silicon layer in a first (memory) area of the substrate and not in a second (logic device) area of the substrate such that the silicon layer is thicker in the first area of the substrate relative to the second area of the substrate. Memory cells are formed in the first area of the substrate, and logic devices are formed in the second area of the substrate.Type: GrantFiled: August 1, 2016Date of Patent: April 25, 2017Assignee: Silicon Storage Technology, Inc.Inventors: Chien Sheng Su, Mandana Tadayoni, Nhan Do
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Publication number: 20170103989Abstract: A method of forming a semiconductor device with memory cells and logic devices on the same silicon-on-insulator substrate. The method includes providing a substrate that includes silicon, a first insulation layer directly over the silicon, and a silicon layer directly over the first insulation layer. Silicon is epitaxially grown on the silicon layer in a first (memory) area of the substrate and not in a second (logic device) area of the substrate such that the silicon layer is thicker in the first area of the substrate relative to the second area of the substrate. Memory cells are formed in the first area of the substrate, and logic devices are formed in the second area of the substrate.Type: ApplicationFiled: August 1, 2016Publication date: April 13, 2017Inventors: CHIEN SHENG SU, MANDANA TADAYONI, NHAN DO
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Patent number: 9570581Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.Type: GrantFiled: April 5, 2016Date of Patent: February 14, 2017Assignee: Silicon Storage Technology, Inc.Inventors: Willem-Jan Toren, Xian Liu, Gerhard Metzger-Brueckl, Nhan Do, Stephan Wege, Nadia Miridi, Chieng-Sheng Su, Cecile Bernardi, Liz Cuevas, Florence Guyot, Yueh-Hsin Chen, Henry Om'mani, Mandana Tadayoni
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Publication number: 20170012049Abstract: A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. A conductive word line gate is disposed over a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The thickness of insulation separating the word line gate from the second portion of the channel region is less than that of insulation separating the floating gate from the erase gate.Type: ApplicationFiled: June 14, 2016Publication date: January 12, 2017Inventors: Jeng-Wei Yang, Man-Tang Wu, Chun-Ming Chen, Mandana Tadayoni, Chien-Sheng Su, Nhan Do
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Patent number: 9431407Abstract: A method of forming a semiconductor device starts with a substrate of silicon, a first insulation layer on the silicon, and a silicon layer on the first insulation layer. The silicon layer and the insulation layer are removed just from a second substrate area. A second insulation layer is formed over the silicon layer in the substrate first area and over the silicon in the second substrate area. A first plurality of trenches is formed in the first substrate area that each extends through all the layers and into the silicon. A second plurality of trenches is formed in the second substrate area that each extends through the second insulation layer and into the silicon. An insulation material is formed in the first and second trenches. Logic devices are formed in the first substrate area, and memory cells are formed in the second substrate area.Type: GrantFiled: September 19, 2014Date of Patent: August 30, 2016Assignee: Silicon Storage Technology, Inc.Inventors: Chien-Sheng Su, Hieu Van Tran, Mandana Tadayoni, Nhan Do, Jeng-Wei Yang
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Publication number: 20160225878Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.Type: ApplicationFiled: April 5, 2016Publication date: August 4, 2016Inventors: Willem-Jan Toren, Xian Liu, Gerhard Metzger-Brueckl, Nhan Do, Stephan Wege, Nadia Miridi, Chieng-Sheng Su, Cecile Bernardi, Liz Cuevas, Florence Guyot, Yueh-Hsin Chen, Henry Om'mani, Mandana Tadayoni
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Patent number: 9330922Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.Type: GrantFiled: March 7, 2012Date of Patent: May 3, 2016Assignee: Silicon Storage Technology, Inc.Inventors: Willem-Jan Toren, Xian Liu, Gerhard Metzger-Brueckl, Nhan Do, Stephan Wege, Nadia Miridi, Chien-Sheng Su, Cecile Bernardi, Liz Cuevas, Florence Guyot, Yueh-Hsin Chen, Henry Om'mani, Mandana Tadayoni
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Patent number: 9306039Abstract: A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.Type: GrantFiled: March 23, 2015Date of Patent: April 5, 2016Assignee: Silicon Storage Technology, Inc.Inventors: Mandana Tadayoni, Nhan Do
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Publication number: 20160086962Abstract: A method of forming a semiconductor device starts with a substrate of silicon, a first insulation layer on the silicon, and a silicon layer on the first insulation layer. The silicon layer and the insulation layer are removed just from a second substrate area. A second insulation layer is formed over the silicon layer in the substrate first area and over the silicon in the second substrate area. A first plurality of trenches is formed in the first substrate area that each extends through all the layers and into the silicon. A second plurality of trenches is formed in the second substrate area that each extends through the second insulation layer and into the silicon. An insulation material is formed in the first and second trenches. Logic devices are formed in the first substrate area, and memory cells are formed in the second substrate area.Type: ApplicationFiled: September 19, 2014Publication date: March 24, 2016Inventors: Chien-Sheng Su, Hieu Van Tran, Mandana Tadayoni, Nhan Do, Jeng-Wei Yang
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Patent number: 9245638Abstract: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the fir region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.Type: GrantFiled: March 17, 2014Date of Patent: January 26, 2016Assignee: Silicon Storage Technology, Inc.Inventors: Nhan Do, Elizabeth A. Cuevas, Yuri Tkachev, Mandana Tadayoni, Henry A. Om'mani
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Publication number: 20150270372Abstract: A transistor and method of making same include a substrate, a conductive gate over the substrate and a channel region in the substrate under the conductive gate. First and second insulating spacers are laterally adjacent to first and second sides of the conductive gate. A source region in the substrate is adjacent to but laterally spaced from the first side of the conductive gate and the first spacer, and a drain region in the substrate is adjacent to but laterally spaced apart from the second side of the conductive gate and the second spacer. First and second LD regions are in the substrate and laterally extend between the channel region and the source or drain regions respectively, each with a portion thereof not disposed under the first and second spacers nor under the conductive gate, and each with a dopant concentration less than that of the source or drain regions.Type: ApplicationFiled: June 8, 2015Publication date: September 24, 2015Inventors: CHIEN-SHENG SU, MANDANA TADAYONI, YUEH-HSIN CHEN
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Publication number: 20150263040Abstract: A semiconductor device having a silicon substrate with a first area including a buried insulation layer with silicon over and under the insulation layer and a second area in which the substrate lacks buried insulation disposed under any silicon. Logic devices are formed in the first area having spaced apart source and drain regions formed in the silicon that is over the insulation layer, and a conductive gate formed over and insulated from a portion of the silicon that is over the insulation layer and between the source and drain regions. Memory cells are formed in the second area that include spaced apart second source and second drain regions formed in the substrate and defining a channel region therebetween, a floating gate disposed over and insulated from a first portion of the channel region, and a select gate disposed over and insulated from a second portion of the channel region.Type: ApplicationFiled: March 17, 2014Publication date: September 17, 2015Applicant: Silicon Storage Technology, Inc.Inventors: Chien-Sheng Su, Hieu Van Tran, Mandana Tadayoni, Nhan Do
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Publication number: 20150200278Abstract: A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.Type: ApplicationFiled: March 23, 2015Publication date: July 16, 2015Inventors: Mandana Tadayoni, Nhan Do
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Patent number: 9018690Abstract: A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.Type: GrantFiled: September 28, 2012Date of Patent: April 28, 2015Assignee: Silicon Storage Technology, Inc.Inventors: Mandana Tadayoni, Nhan Do
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Publication number: 20140273387Abstract: A method of forming an MOS transistor by forming a poly gate over and insulated from a substrate, forming a layer of protective insulation material on the poly gate, and then performing a first implant of dopant material into portions of the substrate adjacent the poly gate, wherein the layer of protective insulation material and the poly gate block most or all of the first implant from reaching a portion of the substrate underneath the poly gate. One or more spacers are then formed adjacent the poly gate, followed by a second implant of dopant material into portions of the substrate adjacent to the one or more spacers.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Chien-Sheng Su, Jeng-Wei Yang, Mandana Tadayoni, Yueh-Hsin Chen
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Patent number: 8785307Abstract: A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.Type: GrantFiled: August 23, 2012Date of Patent: July 22, 2014Assignee: Silicon Storage Technology, Inc.Inventors: Xian Liu, Mandana Tadayoni, Chien-Sheng Su, Nhan Do
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Publication number: 20140198578Abstract: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.Type: ApplicationFiled: March 17, 2014Publication date: July 17, 2014Applicant: Silicon Storage Technology, Inc.Inventors: Nhan Do, Elizabeth A. Cuevas, Yuri Tkachev, Mandana Tadayoni, Henry A. Om'mani
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Patent number: 8711636Abstract: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.Type: GrantFiled: May 3, 2012Date of Patent: April 29, 2014Assignee: Silicon Storage Technology, Inc.Inventors: Nhan Do, Elizabeth A. Cuevas, Yuri Tkachev, Mandana Tadayoni, Henry A. Om'Mani
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Publication number: 20140091382Abstract: A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Mandana Tadayoni, Nhan Do