Patents by Inventor Mandar R. Ranade

Mandar R. Ranade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for reducing leakage power of a circuit
    Patent number: 9921630
    Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Gururaj K. Shamanna, Stefan Rusu, Phani Kumar Kandula, Sankalan Prasad, Mandar R. Ranade, Narayanan Natarajan, Tessil Thomas
  • APPARATUS AND METHOD FOR REDUCING LEAKAGE POWER OF A CIRCUIT
    Publication number: 20160077567
    Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.
    Type: Application
    Filed: November 20, 2015
    Publication date: March 17, 2016
    Inventors: Gururaj K. Shamanna, Stefan Rusu, Phani Kumar Kandula, Sankalan Prasad, Mandar R. Ranade, Narayanan Natarajan, Tessil Thomas
  • Apparatus and method for reducing leakage power of a circuit
    Patent number: 9207750
    Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: December 8, 2015
    Assignee: Intel Corporation
    Inventors: Gururaj K. Shamanna, Stefan Rusu, Phani Kumar Kandula, Sankalan Prasad, Mandar R. Ranade, Narayanan Natarajan, Tessil Thomas
  • APPARATUS AND METHOD FOR REDUCING LEAKAGE POWER OF A CIRCUIT
    Publication number: 20140173317
    Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Inventors: Gururaj K. Shamanna, Stefan Rusu, Phani Kumar Kandula, Sankalan Prasad, Mandar R. Ranade, Narayanan Natarajan, Tessil Thomas