Patents by Inventor Mandar S. Joshi
Mandar S. Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10361933Abstract: An apparatus and method for a power-efficient framework to maintain data synchronization of a mobile personal computer (MPC) are described. In one embodiment, the method includes the detection of a data synchronization wakeup event while the MPC is operating according to a sleep state. Subsequent to wakeup event, at least one system resource is disabled to provide a minimum number of system resources required to re-establish a network connection. In one embodiment, user data from a network server is synchronized on the MPC without user intervention; the mobile platform system resumes operation according to the sleep state. In one embodiment, a wakeup alarm is programmed according to a user history profile regarding received e-mails. In a further embodiment, data synchronizing involves disabling a display, and throttling the system processor to operate at a reduced frequency. Other embodiments are described and claimed.Type: GrantFiled: September 25, 2015Date of Patent: July 23, 2019Assignee: Intel CorporationInventors: Shobhit Varshney, Prashant Gandhi, Mandar S. Joshi, Uttam K. Sengupta, Shreekant S. Thakkar
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Patent number: 10339935Abstract: Techniques are provided for training of a text independent (TI) speaker recognition (SR) model. A methodology implementing the techniques according to an embodiment includes measuring context data associated with collected TI speech utterances from a user and identifying the user based on received identity measurements. The method further includes performing a speech quality analysis and a speaker state analysis based on the utterances, and evaluating a training merit value of the utterances, based on the speech quality analysis and the speaker state analysis. If the training merit value exceeds a threshold value, the utterances are stored as training data in a training database. The database is indexed by the user identity and the context data. The method further includes determining whether the stored training data has achieved a sufficiency level for enrollment of a TI SR model, and training the TI SR model for the identified user and context.Type: GrantFiled: June 19, 2017Date of Patent: July 2, 2019Assignee: INTEL CORPORATIONInventors: Gokcen Cilingir, Jonathan J. Huang, Narayan Biswal, Mandar S. Joshi
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Publication number: 20180366124Abstract: Techniques are provided for training of a text independent (TI) speaker recognition (SR) model. A methodology implementing the techniques according to an embodiment includes measuring context data associated with collected TI speech utterances from a user and identifying the user based on received identity measurements. The method further includes performing a speech quality analysis and a speaker state analysis based on the utterances, and evaluating a training merit value of the utterances, based on the speech quality analysis and the speaker state analysis. If the training merit value exceeds a threshold value, the utterances are stored as training data in a training database. The database is indexed by the user identity and the context data. The method further includes determining whether the stored training data has achieved a sufficiency level for enrollment of a TI SR model, and training the TI SR model for the identified user and context.Type: ApplicationFiled: June 19, 2017Publication date: December 20, 2018Applicant: INTEL CORPORATIONInventors: Gokcen Cilingir, Jonathan J. Huang, Narayan Biswal, Mandar S. Joshi
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Patent number: 9852731Abstract: Technologies are described herein that allow a user to wake up a computing device operating in a low-power state and for the user to be verified by speaking a single wake phrase. Wake phrase recognition is performed by a low-power engine. In some embodiments, the low-power engine may also perform speaker verification. In other embodiments, the mobile device wakes up after a wake phrase is recognized and a component other than the low-power engine performs speaker verification on a portion of the audio input comprising the wake phrase. More than one wake phrases may be associated with a particular user, and separate users may be associated with different wake phrases. Different wake phrases may cause the device transition from a low-power state to various active states.Type: GrantFiled: July 29, 2016Date of Patent: December 26, 2017Assignee: Intel CorporationInventors: Saurabh Dadu, Lakshman Krishnamurthy, Francis M. Tharappel, Prabhakar R. Datta, Bryan R. Peebler, Michael E. Deisher, Mandar S. Joshi, Saurin Shah, Brian K. Vogel
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Publication number: 20170263254Abstract: A voice command device (VCD) has privacy protection. The VCD comprises a processor, first and second input devices, at least one data line to couple the first and second input devices to the processor, a power supply, and a sensor power line to couple the first and second input devices to the power supply. The VCD also comprises a manually operated mechanical switch on the sensor power line, to divide the sensor power line into a first leg comprising the power supply and a second leg comprising the input devices. The VCD also comprises an active sensor indicator light on the second leg of the sensor power line. The indicator light is configured to indicate whether the input devices are operational, based on a power level of the second leg of the sensor power line. Other embodiments are described and claimed.Type: ApplicationFiled: March 10, 2016Publication date: September 14, 2017Applicant: lntel IP CorporationInventors: PRASHANT DEWAN, UTTAM K. SENGUPTA, SATISH KUMAR L. BHRUGUMALLA, MANDAR S. JOSHI
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Publication number: 20170032784Abstract: Technologies are described herein that allow a user to wake up a computing device operating in a low-power state and for the user to be verified by speaking a single wake phrase. Wake phrase recognition is performed by a low-power engine. in some embodiments, the low-power engine may also perform speaker verification. In other embodiments, the mobile device wakes up after a wake phrase is recognized and a component other than the low-power engine performs speaker verification on a portion of the audio input comprising the wake phrase, More than one wake phrases may be associated with a particular user, and separate users may be associated with different wake phrases. Different wake phrases may cause the device transition from a low-power state to various active states.Type: ApplicationFiled: July 29, 2016Publication date: February 2, 2017Inventors: Saurabh Dadu, Lakshman Krishnamurthy, Francis M. Tharappel, Prabhakar R. Datta, Bryan R. Peebler, Michael E. Deisher, Mandar S. Joshi, Saurin Shah, Brian K. Vogel
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Patent number: 9445209Abstract: Technologies are described herein that allow a user to wake up a computing device operating in a low-power state and for the user to be verified by speaking a single wake phrase. Wake phrase recognition is performed by a low-power engine. In some embodiments, the low-power engine may also perform speaker verification. In other embodiments, the mobile device wakes up after a wake phrase is recognized and a component other than the low-power engine performs speaker verification on a portion of the audio input comprising the wake phrase. More than one wake phrases may be associated with a particular user, and separate users may be associated with different wake phrases. Different wake phrases may cause the device transition from a low-power state to various active states.Type: GrantFiled: July 11, 2013Date of Patent: September 13, 2016Assignee: Intel CorporationInventors: Saurabh Dadu, Lakshman Krishnamurthy, Francis M. Tharappel, Prabhakar R. Datta, Bryan R. Peebler, Michael E. Deisher, Mandar S. Joshi, Saurin Shah, Brian K. Vogel
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Publication number: 20150245154Abstract: Technologies are described herein that allow a user to wake up a computing device operating in a low-power state and for the user to be verified by speaking a single wake phrase. Wake phrase recognition is performed by a low-power engine. In some embodiments, the low-power engine may also perform speaker verification. In other embodiments, the mobile device wakes up after a wake phrase is recognized and a component other than the low-power engine performs speaker verification on a portion of the audio input comprising the wake phrase. More than one wake phrases may be associated with a particular user, and separate users may be associated with different wake phrases. Different wake phrases may cause the device transition from a low-power state to various active states.Type: ApplicationFiled: July 11, 2013Publication date: August 27, 2015Inventors: Saurabh Dadu, Lakshman Krishnamurthy, Francis M. Tharappel, Prabhakar R. Datta, Bryan R. Peebler, Michael E. Deisher, Mandar S. Joshi, Saurin Shah, Brian K. Vogel
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Publication number: 20150221307Abstract: Disclosed are embodiments for seamless, single-step, and speech-triggered transition of a host processor and/or computing device from a low functionality mode to a high functionality mode in which full vocabulary speech recognition can be accomplished. First audio samples are captured by a low power audio processor while the host processor is in a low functionality mode. The low power audio processor may identify a predetermined audio pattern. The low power audio processor, upon identifying the predetermined audio pattern, triggers the host processor to transition to a high functionality mode. An end portion of the first audio samples that follow an end-point of the predetermined audio pattern may be stored in system memory accessible by the host processor. Second audio samples are captured and stored with the end portion of the first audio samples.Type: ApplicationFiled: December 20, 2013Publication date: August 6, 2015Inventors: Saurin Shah, Bryan R. Peebler, Francis M. Tharappel, Saurabh Dadu, Pierre-Louis Bossart, Devon Worrell, Edward V. Gamsaragan, Ivan Le Hin, Rakesh A. Ughreja, Singaravelan Nallasellan, Mandar S. Joshi, Ohad Falik
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Patent number: 7319947Abstract: A method and apparatus for performing distributed simulation is presented. According to an embodiment of the present invention, simulators are interfaced to a simulation backplane via simulator-dependent interfaces (SDI's). The simulators exchange messages via the simulation backplane and the SDI's. The SDI's convert the exchanged messages between a data format supported by the backplane and a data format supported by the simulator to which the interface is connected. By interfacing the simulators with the backplane via SDI's, the validation environment may be changed without reconfiguring the backplane.Type: GrantFiled: December 22, 1999Date of Patent: January 15, 2008Assignee: Intel CorporationInventors: Manpreet S. Khaira, Erik M. Seligman, Jeremy S. Casas, Steve W. Otto, Mandar S. Joshi
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Patent number: 7171347Abstract: A method of preparing a circuit model for simulation comprises decomposing the circuit model having a number of latches into a plurality of extended latch boundary components and partitioning the plurality of extended latch boundary components. Decomposing and partitioning the circuit model may include decomposing hierarchical cells of the circuit model, and using a constructive bin-packing heuristic to partition the plurality of extended latch boundary components. The partitioned circuit model is compiled, and simulated on a uni-processor, a multi-processor, or a distributed processing computer system.Type: GrantFiled: July 2, 1999Date of Patent: January 30, 2007Assignee: Intel CorporationInventors: Manpreet S. Khaira, Steve W. Otto, Honghua H. Yang, Mandar S. Joshi, Jeremy S. Casas, Erik M. Seligman
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Publication number: 20030163297Abstract: A method of preparing a circuit model for simulation comprises decomposing the circuit model having a number of latches into a plurality of extended latch boundary components and partitioning the plurality of extended latch boundary components. Decomposing and partitioning the circuit model may include decomposing hierarchical cells of the circuit model, and using a constructive bin-packing heuristic to partition the plurality of extended latch boundary components. The partitioned circuit model is compiled, and simulated on a uni-processor, a multi-processor, or a distributed processing computer system.Type: ApplicationFiled: July 2, 1999Publication date: August 28, 2003Inventors: MANPREET S. KHAIRA, STEVE W. OTTO, HONGHUA H. YANG, MANDAR S. JOSHI, JEREMY S. CASAS, ERIK M. SELIGMAN
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Patent number: 6198684Abstract: In one embodiment, a memory cell having a first port and a second port is provided. A first word line is associated with the first port, and a second word line is associated with the second port. A first driver is associated with the first word line, and a second driver is associated with the second word line. A decoder is associated with the first and second drivers.Type: GrantFiled: December 23, 1999Date of Patent: March 6, 2001Assignee: Intel CorporationInventors: Kevin X. Zhang, Thomas D. Fletcher, Mandar S. Joshi
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Patent number: 6006299Abstract: In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A lock bit is set when the first processor begins execution of the first instruction. Thereupon, the second processor is prevented from executing its instruction until the first processor has completed its processing of the shared data. Hence, the second processor queues its request in a buffer. The lock bit is cleared after the first processor has completed execution of its instruction. The first processor then checks the buffer for any outstanding requests. In response to the second processor's queued request, the first processor transmits a signal to the second processor indicating that the data is now not locked.Type: GrantFiled: March 1, 1994Date of Patent: December 21, 1999Assignee: Intel CorporationInventors: Wen-Hann Wang, Konrad K. Lai, Gurbir Singh, Mandar S. Joshi, Nitin V. Sarangdhar, Matthew A. Fisch
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Patent number: 5715428Abstract: A computer system comprising a plurality of caching agents with a cache hierarchy, the caching agents sharing memory across a system bus and issuing memory access requests in accordance with a protocol wherein a line of a cache has a present state comprising one of a plurality of line states. The plurality of line states includes a modified (M) state, wherein a line of a first caching agent in M state has data which is more recent than any other copy in the system; an exclusive (E) state, wherein a line in E state in a first caching agent is the only one of the agents in the system which has a copy of the data in a line of the cache, the first caching agent modifying the data in the cache line independent of other said agents coupled to the system bus; a shared (S) state, wherein a line in S state indicates that more than one of the agents has a copy of the data in the line; and an invalid (I) state indicating that the line does not exist in the cache.Type: GrantFiled: April 29, 1996Date of Patent: February 3, 1998Assignee: Intel CorporationInventors: Wen-Hann Wang, Konrad K. Lai, Gurbir Singh, Michael W. Rhodehamel, Nitin V. Sarangdhar, John M. Bauer, Mandar S. Joshi, Ashwani K. Gupta
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Patent number: 5680572Abstract: A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress.Type: GrantFiled: July 15, 1996Date of Patent: October 21, 1997Assignee: Intel CorporationInventors: Haitham Akkary, Jeffrey M. Abramson, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland, Mandar S. Joshi, Brent E. Lince
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Patent number: 5671444Abstract: A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress.Type: GrantFiled: October 15, 1996Date of Patent: September 23, 1997Assignee: Intel CorporaitonInventors: Haitham Akkary, Jeffrey M. Abramson, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland, Mandar S. Joshi, Brent E. Lince
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Patent number: 5630075Abstract: A microprocessor having a bus for the transmission of data, an execution unit for processing data and instructions, a memory for storing data and instructions, and a write combining buffer for combining data of at least two write commands into a single data set, wherein the combined data set is transmitted over the bus in one clock cycle rather than two or more clock cycles. Thereby, buss traffic is minimized. The write combining buffer is comprised of a single line having a 32-byte data portion, a tag portion, and a validity portion. The tag entry specifies the address corresponding to the data currently stored in the data portion. There is one valid bit corresponding to each byte of the data portion which specifies whether that byte currently contains useful data. So long as subsequent write operations to the write combining buffer result in hits, the data is written to the buffer's data portion. But when a miss occurs, the line is reallocated, and the old data is written to the main memory.Type: GrantFiled: May 25, 1995Date of Patent: May 13, 1997Assignee: Intel CorporationInventors: Mandar S. Joshi, Andrew F. Glew, Nitin V. Sarangdhar
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Patent number: 5526510Abstract: The data cache unit includes a separate fill buffer and a separate write-back buffer. The fill buffer stores one or more cache lines for transference into data cache banks of the data cache unit. The write-back buffer stores a single cache line evicted from the data cache banks prior to write-back to main memory. Circuitry is provided for transferring a cache line from the fill buffer into the data cache banks while simultaneously transferring a victim cache line from the data cache banks into the write-back buffer. Such allows the overall replace operation to be performed in only a single clock cycle. In a particular implementation, the data cache unit is employed within a microprocessor capable of speculative and out-of-order processing of memory instructions. Moreover, the microprocessor is incorporated within a multiprocessor computer system wherein each microprocessor is capable of snooping the cache lines of data cache units of each other microprocessor. The data cache unit is also a non-blocking cache.Type: GrantFiled: September 30, 1994Date of Patent: June 11, 1996Assignee: Intel CorporationInventors: Haitham Akkary, Mandar S. Joshi, Rob Murray, Brent E. Lince, Paul D. Madland, Andrew F. Glew, Glenn J. Hinton