Abstract: The disclosure is directed to the use of an externally-supplied control current to control the adjustment of an internal supply voltage generated via voltage regulator circuitry, which may be identified with an integrated circuit (IC) chip. The configuration of the voltage regulator circuitry functions to establish a linear relationship between the control current and the internal voltage supply. This configuration enables setting the control current to a predetermined value, causing the supply voltage to deviate in a predictable and controllable manner, and thus facilitating verification of the IC chip's internal voltage supply test circuitry. Furthermore, because the control current used for this purpose is relatively small (e.g. on the order of microamps), existing on chip test architecture, which may accommodate such low level currents, may be re-used for the selective routing of the control current for such IC testing.

Abstract: The disclosure is directed to the use of an externally-supplied control current to control the adjustment of an internal supply voltage generated via voltage regulator circuitry, which may be identified with an integrated circuit (IC) chip. The configuration of the voltage regulator circuitry functions to establish a linear relationship between the control current and the internal voltage supply. This configuration enables setting the control current to a predetermined value, causing the supply voltage to deviate in a predictable and controllable manner, and thus facilitating verification of the IC chip's internal voltage supply test circuitry. Furthermore, because the control current used for this purpose is relatively small (e.g. on the order of microamps), existing on chip test architecture, which may accommodate such low level currents, may be re-used for the selective routing of the control current for such IC testing.

Abstract: The present disclosure relate to a sensor system having a low offset error. In some embodiments, the sensor system comprises a sensor configured to generate a sensor signal, which is provided to a main signal path having a first chopping correction circuit and a second chopping correction circuit. The first and second chopping correction circuit chop the sensor signal at first and second frequencies to reduce offset errors, but in doing so generate first and second chopping ripple errors. A first digital offset feedback loop generates a first compensation signal, which is fed back into the main signal path to mitigate the first chopping ripple error. A second digital offset feedback loop generates a second compensation signal, which is fed back into the main signal path to mitigate the second chopping ripple error.

Abstract: The present disclosure relate to a sensor system having a low offset error. In some embodiments, the sensor system comprises a sensor configured to generate a sensor signal, which is provided to a main signal path having a first chopping correction circuit and a second chopping correction circuit. The first and second chopping correction circuit chop the sensor signal at first and second frequencies to reduce offset errors, but in doing so generate first and second chopping ripple errors. A first digital offset feedback loop generates a first compensation signal, which is fed back into the main signal path to mitigate the first chopping ripple error. A second digital offset feedback loop generates a second compensation signal, which is fed back into the main signal path to mitigate the second chopping ripple error.

Abstract: The present disclosure relate to a sensor system having a low offset error. In some embodiments, the sensor system comprises a sensor configured to generate a sensor signal, which is provided to a main signal path having a first chopping correction circuit and a second chopping correction circuit. The first and second chopping correction circuit chop the sensor signal at first and second frequencies to reduce offset errors, but in doing so generate first and second chopping ripple errors. A first digital offset feedback loop generates a first compensation signal, which is fed back into the main signal path to mitigate the first chopping ripple error. A second digital offset feedback loop generates a second compensation signal, which is fed back into the main signal path to mitigate the second chopping ripple error.

Abstract: The present disclosure relate to a sensor system having a low offset error. In some embodiments, the sensor system comprises a sensor configured to generate a sensor signal, which is provided to a main signal path having a first chopping correction circuit and a second chopping correction circuit. The first and second chopping correction circuit chop the sensor signal at first and second frequencies to reduce offset errors, but in doing so generate first and second chopping ripple errors. A first digital offset feedback loop generates a first compensation signal, which is fed back into the main signal path to mitigate the first chopping ripple error. A second digital offset feedback loop generates a second compensation signal, which is fed back into the main signal path to mitigate the second chopping ripple error.

Abstract: An analog-to-digital converter comprising a capacitor array having a plurality of unit capacitors, each having first and second inputs; a comparator having a pair of inputs and at least one output; and a controller configured to couple one input of each unit capacitor of the plurality of capacitors to the inputs of the comparator, and to control a feedback loop between the pair of inputs and the at least one output of the comparator.

Abstract: An analog-to-digital converter comprising a capacitor array having a plurality of unit capacitors, each having first and second inputs; a comparator having a pair of inputs and at least one output; and a controller configured to couple one input of each unit capacitor of the plurality of capacitors to the inputs of the comparator, and to control a feedback loop between the pair of inputs and the at least one output of the comparator.