Abstract: By using a basic cell (g), an overall array (ga) for forming n products from pairs of multidigit binary numbers Amn, Bkn and for adding these n products is formed, with the formation and summation of all partial products being interleaved row by row. Each basic cell contains a delay unit for the A-coefficient inputs controlled by a half clock signal, an undelayed through connection for the B-coefficient input, an added fed via respective delay units with a sum input, a carry input, and a summation input, and a logic gate which combines the B-coefficient with the undelayed A-coefficients to form the partial product thereof and provides the partial product to the summation input of the adder.

Abstract: A two-phase clock generator generates a nonoverlapping two-phase clock from a unipolar input clock by utilizing gate delays in first and second signal paths. The output of each signal path is fed over a cross-coupled feedback path back to a logic gate in the respective other signal path. Each logic gate is a floating inverter having a first supply terminal connected to a supply voltage, and having a second supply terminal that is the feed point for the respective feedback signal from the output of the other signal path.

Abstract: A CMOS inverter chain includes the alternating series connection of N- and P-inverters. An N-inverter is a conventional type of CMOS inverter employing an N-intermediate transistor between both the P- and the N-transistor; a P-inverter, however, is a CMOS inverter employing a P-intermediate transistor between both the P- and the N-transistor. The gates of the intermediate transistors are interconnected and controlled by the clock signal, whereas the inverter input is constituted by the interconnected gates of the P- and the N-transistor of each inverter. Such an inverter chain can be used, for example, as a digital pulse width discriminator, as a final position counter, as a circuit for compensating signal drop-outs in input pulses, or else for effecting ring oscillator synchronizations.

Abstract: The circuit contains three multipliers/adders for the luminance signal (y) and the two color-difference signals (r-y, b-y). For the output signals of these stages, four parallel adders are provided. The multipliers for the factors -0.51 and -0.19, which would be required in accordance with the color-television-system formula y=0.3r+0.59g+0.11b are rendered unnecessary because, among other things, the input signals are provided with correction factors (k, L, m) and correction addends (d, e, f) in the multipliers/adders in view of a presettable color overload.

Abstract: An input circuit of a bucket brigade circuit consists of an input transistor and an input capacitor. The input capacitor is shunting the drain-source path of the input transistor.

Abstract: Two-dimensional analog memory monolithically integrated with insulated-gate field-effect transistors, operating on the charge-transfer, and more particularly on the bucket-brigade principle, for temporarily storing the signals originating with the two half pictures of a (TV) video signal.

Abstract: To reduce the D.C drift of bucket-brigade devices having common output circuits (emitter follower), an output circuit is provided having an additional transistor and an additional capacitor. The terminal on the gate side of the capacitor associated with the last delaying transistor is not connected to the gate terminal but to the source terminal of the output transistor, the gate terminal of the terminating transistor is applied via the additional capacitor to that particular clock signal to which the penultimate delaying transistor is applied, and the drain terminal of the terminating transistor, via an enhancement-type transistor of the same conductivity, connected as a diode by directly connecting both the drain and the gate terminals, is connected to the gate terminal thereof.

Abstract: This relates to apparatus for the "picture on picture" or "program check" project. Storage, storage control circuits and clock signal generators are disclosed. The storage consists of two parts which are simultaneously fed by selected lines of the second program.