Patents by Inventor Manfred Hauf

Manfred Hauf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6620724
    Abstract: Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: September 16, 2003
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Uwe Schroeder, Helmut Horst Tews, Irene McStay, Manfred Hauf, Matthias Goldbach, Bernhard Sell, Harald Seidl, Dirk Schumann, Rajarao Jammy, Joseph F. Shepard, Jr., Jean-Marc Rousseau
  • Patent number: 6483172
    Abstract: A process for fabricating a device including the step of forming a structure for facilitating the passivation of surface states is disclosed. The structure comprises an oxynitride layer formed as part of the device structure. The oxynitride facilitates the passivation of surface states when heated.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: November 19, 2002
    Assignees: Siemens Aktiengesellschaft, International Business Machines Corporation
    Inventors: Donna Rizzone Cote, William Joseph Cote, Son Van Nguyen, Markus Kirchhoff, Max G. Levy, Manfred Hauf
  • Patent number: 5824580
    Abstract: A Field Effect Transistor (FET) and a method of forming FETs on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. A gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide. Preferably, potassium is introduced during Chem-Mech polish when the trenches are filled with polysilicon. A slurry containing KOH is used to polish the polysilicon and the potassium diffuses from the slurry along the ONO layer. After Chem-Mech polish, the poly in the trenches is recessed by Reactive Ion Etching (RIE) it below the wafer surface. Optionally, after RIE, the wafer may be dipped in a KOH solution. Next, an oxide collar is formed along the ONO layer in the trenches above the recessed polysilicon.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: October 20, 1998
    Assignees: International Business Machines Corporation, Siemens Aktiengesellschaft
    Inventors: Manfred Hauf, Max G. Levy, Victor Ray Nastasi
  • Patent number: 5757059
    Abstract: An FET isolated on either side by a trench. The FET has a dielectric layer in the isolating trench along at least one side. The dielectric layer which may be an ONO layer has an oxidation catalyst diffused into it. The oxidation catalyst may be potassium. A gate oxide along the side of the FET in close proximity to the ONO layer is thicker than gate oxide between both sides.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: May 26, 1998
    Assignee: International Business Machines Corporation
    Inventors: Manfred Hauf, Max G. Levy, Victor Ray Nastasi
  • Patent number: 5721448
    Abstract: An integrated circuit with FETs having an essentially uniform gate oxide thickness and FETs having gate oxide thickness enhanced along the sides. FETs with enhanced gate oxide have an ONO layer diffused with potassium in close proximity to the enhanced (thicker) oxide, and, as a result, have a slightly higher V.sub.t and much more attenuated soft turn on.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: February 24, 1998
    Assignee: International Business Machines Corporation
    Inventors: Manfred Hauf, Max G. Levy, Victor Ray Nastasi