Patents by Inventor Manfred Horstmann

Manfred Horstmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8440516
    Abstract: A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: May 14, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Thorsten Kammler, Jan Hoentschel, Manfred Horstmann
  • Patent number: 8288256
    Abstract: By combining an anneal process for adjusting the effective channel length and a substantially diffusion-free anneal process performed after a deep drain and source implantation, the vertical extension of the drain and source region may be increased substantially without affecting the previously adjusted channel length. In this manner, in SOI devices, the drain and source regions may extend down to the buried insulating layer, thereby reducing the parasitic capacitance, while the degree of dopant activation and thus series resistance in the extension regions may be improved. Furthermore, less critical process parameters during the anneal process for adjusting the channel length may provide the potential for reducing the lateral dimensions of the transistor devices.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: October 16, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas Feudel, Rolf Stephan, Manfred Horstmann
  • Patent number: 8274120
    Abstract: By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: September 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Thorsten Kammler, Jan Hoentschel, Manfred Horstmann, Peter Javorka, Joe Bloomquist
  • Publication number: 20120161240
    Abstract: When incorporating a strain-inducing semiconductor alloy in one type of sophisticated transistors, the removal of sacrificial cap materials, such as a spacer layer, sacrificial spacer elements and dielectric cap materials, may be accomplished by using, at least in a first phase of the removal process, an efficient etch stop liner material, which may thus reduce the material loss in the drain and source extension regions that are formed prior to the deposition of the strain-inducing semiconductor material. Moreover, the drain and source extension regions of the other type of transistor may be formed with superior process uniformity due to a reduced material erosion of the corresponding spacer elements.
    Type: Application
    Filed: December 27, 2011
    Publication date: June 28, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stephan Kronholz, Juergen Amon, Manfred Horstmann
  • Patent number: 8188871
    Abstract: In a memory cell, the drive current capabilities of the transistors may be adjusted by locally providing an increased gate dielectric thickness and/or gate length of one or more of the transistors of the memory cell. That is, the gate length and/or the gate dielectric thickness may vary along the transistor width direction, thereby providing an efficient mechanism for adjusting the effective drive current capability while at the same time allowing the usage of a simplified geometry of the active region, which may result in enhanced production yield due to enhanced process uniformity. In particular, the probability of creating short circuits caused by nickel silicide portions may be reduced.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: May 29, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Manfred Horstmann, Patrick Press, Karsten Wieczorek, Kerstin Ruttloff
  • Patent number: 8138571
    Abstract: By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: March 20, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Christoph Schwan, Joe Bloomquist, Peter Javorka, Manfred Horstmann, Sven Beyer, Markus Forsberg, Frank Wirbeleit, Karla Romero
  • Patent number: 8101512
    Abstract: In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: January 24, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Martin Gerhardt, Martin Trentzsch, Markus Forsberg, Manfred Horstmann
  • Patent number: 8097542
    Abstract: In a dual stress liner approach, an intermediate etch stop material may be provided on the basis of a plasma-assisted oxidation process rather than by deposition so the corresponding thickness of the etch stop material may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional strategies, thereby reducing deposition-related irregularities which may translate into a significant reduction of yield loss, in particular for highly scaled semiconductor devices.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: January 17, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Karsten Wieczorek, Manfred Horstmann, Peter Huebler, Kerstin Ruttloff
  • Patent number: 8039335
    Abstract: By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: October 18, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sven Beyer, Manfred Horstmann, Patrick Press, Wolfgang Buchholtz
  • Patent number: 8039338
    Abstract: By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Manfred Horstmann, Peter Javorka, Karsten Wieczorek, Kerstin Ruttloff
  • Patent number: 7999326
    Abstract: By embedding a silicon/germanium mixture in a silicon layer of high tensile strain, a moderately high degree of tensile strain may be maintained in the silicon/germanium mixture, thereby enabling increased performance of N-channel transistors on the basis of silicon/germanium material. In other regions, the germanium concentration may be varied to provide different levels of tensile or compressive strain.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: August 16, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Karla Romero, Manfred Horstmann
  • Patent number: 7955937
    Abstract: By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: June 7, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Manfred Horstmann, Thomas Feudel, Thomas Heller
  • Publication number: 20110104878
    Abstract: By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.
    Type: Application
    Filed: January 13, 2011
    Publication date: May 5, 2011
    Inventors: Sven Beyer, Manfred Horstmann, Patrick Press, Wolfgang Buchholtz
  • Patent number: 7906383
    Abstract: By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: March 15, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ralf Richter, Andy Wei, Manfred Horstmann, Joerg Hohage
  • Patent number: 7893503
    Abstract: By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: February 22, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sven Beyer, Manfred Horstmann, Patrick Press, Wolfgang Buchholtz
  • Patent number: 7863171
    Abstract: By introducing a atomic species, such as carbon, fluorine and the like, into the drain and source regions, as well as in the body region, the junction leakage of SOI transistors may be significantly increased, thereby providing an enhanced leakage path for accumulated minority charge carriers. Consequently, fluctuations of the body potential may be significantly reduced, thereby improving the overall performance of advanced SOI devices. In particular embodiments, the mechanism may be selectively applied to threshold voltage sensitive device areas, such as static RAM areas.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: January 4, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jan Hoentschel, Andy Wei, Joe Bloomquist, Manfred Horstmann
  • Patent number: 7829421
    Abstract: By forming a portion of a PN junction within strained silicon/germanium material in SOI transistors with a floating body architecture, the junction leakage may be significantly increased, thereby reducing floating body effects. The positioning of a portion of the PN junction within the strained silicon/germanium material may be accomplished on the basis of implantation and anneal techniques, contrary to conventional approaches in which in situ doped silicon/germanium is epitaxially grown so as to form the deep drain and source regions. Consequently, high drive current capability may be combined with a reduction of floating body effects.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: November 9, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Thorsten Kammler, Jan Hoentschel, Manfred Horstmann
  • Patent number: 7816199
    Abstract: A method of forming a semiconductor structure includes providing a substrate having a first feature and a second feature. A mask is formed over the substrate. The mask covers the first feature. An ion implantation process is performed to introduce ions of a non-doping element into the second feature. The mask is adapted to absorb ions impinging on the first feature. After the ion implantation process, an annealing process is performed.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: October 19, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas Feudel, Manfred Horstmann, Andreas Gehring
  • Publication number: 20100203698
    Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.
    Type: Application
    Filed: April 20, 2010
    Publication date: August 12, 2010
    Inventors: Frank Wirbeleit, Rolf Stephan, Manfred Horstmann
  • Publication number: 20100187635
    Abstract: By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.
    Type: Application
    Filed: April 6, 2010
    Publication date: July 29, 2010
    Inventors: SVEN BEYER, Manfred Horstmann, Patrick Press, Wolfgang Buchholtz