Abstract: A time-to-digital converter circuit is disclosed, the time-to-digital converter circuit including a plurality of delay stages connected to form a delay line, a plurality of event counters, an encoder circuit for triggering the delay line, and a binning circuit for associating an event with an event counter from plurality of event counters. The binning circuit selects the event counter based on a signal from the delay line, and wherein the encoder circuit is configured to sequentially trigger a different delay stage of the plurality of delay stages. Also disclosed is a time-of-flight sensor implementing the time-to-digital converter circuit, and an associated apparatus and method.

Abstract: A semiconductor body includes a driver for driving a light source, at least two detectors each including an avalanche diode, a time-to-digital converter arrangement coupled to outputs of the at least two detectors, a memory that is coupled to the time-to-digital converter arrangement and is configured to store at least one histogram, and an evaluation unit coupled to the driver and to the memory.

Abstract: Methods for detecting a time-of-flight include: emitting a light pulse toward a target; detecting a presence of light received at a light detector; obtaining a delay time between emitting the light pulse and detecting the presence of the light at the light detector; responsive to obtaining the delay time, (a) updating an overall intensity counter that counts a total number of delay times that have been obtained and (b) updating a delay time counter out of a plurality of different delay time counters, wherein each delay time counter counts a total number of delay times obtained that have a corresponding delay time value; and monitoring a threshold of each delay time counter to determine whether a threshold value is exceeded.

Abstract: A driving circuit (10) to generate a signal pulse for operating a light-emitting diode (20) comprises an external terminal (LEDK, LEDA) to connect the light-emitting diode (20) to the driving circuit (10). In a first operating state/pre-charge state of the driving circuit (10), a first controllable switching circuit (100) connects a first side (301) of a capacitor (300) to a reference potential (Vref) and a second controllable switch (200) connects a second side (302) of the capacitor (300) to one of a supply and ground potential (VDD, VSS). In a second operating state of the driving circuit (10), the first controllable switching circuit (100) connects the first side (301) of the capacitor (300) to said one of the supply and ground potential (VDD, VSS) and the second controllable switch (200) connects the second side (302) of the capacitor (300) to the external terminal (LEDK, LEDA) to provide a signal pulse for operating the light emitting diode.

Abstract: Illuminator modules having improved safety features are described. In some implementations, light to be emitted from a module is produced by a light source, and light reflected by an optical component disposed over the light source is detected by a photodetectors. A distribution of the reflected light detected by the photodetectors is monitored, and an optical output power of the light source is regulated if it is determined, based on the monitored distribution of light, that an unsafe level of light may be emitted from the module.

Abstract: A voltage converter includes a first to a third capacitor, a supply terminal, a first and a second clock terminal and a transfer arrangement, wherein a first electrode of the first capacitor is connected to the first clock terminal and a second electrode of the first capacitor is connected to a first node of the transfer arrangement, wherein a first electrode of the second capacitor is connected to the second clock terminal and a second electrode of the second capacitor is connected to a second node of the transfer arrangement, and wherein a first electrode of the third capacitor is permanently and directly connected to the second electrode of the first capacitor and a second electrode of the third capacitor is connected to a third node of the transfer arrangement.

Abstract: A driving circuit (10) to generate a signal pulse for operating a light-emitting diode (20) comprises an external terminal (LEDK, LEDA) to connect the light-emitting diode (20) to the driving circuit (10). In a first operating state/pre-charge state of the driving circuit (10), a first controllable switching circuit (100) connects a first side (301) of a capacitor (300) to a reference potential (Vref) and a second controllable switch (200) connects a second side (302) of the capacitor (300) to one of a supply and ground potential (VDD, VSS). In a second operating state of the driving circuit (10), the first controllable switching circuit (100) connects the first side (301) of the capacitor (300) to said one of the supply and ground potential (VDD, VSS) and the second controllable switch (200) connects the second side (302) of the capacitor (300) to the external terminal (LEDK, LEDA) to provide a signal pulse for operating the light emitting diode.

Abstract: A semiconductor body comprises a driver for driving a light source, at least two detectors each comprising an avalanche diode, a time-to-digital converter arrangement coupled to outputs of the at least two detectors, a memory that is coupled to the time-to-digital converter arrangement and is configured to store at least one histogram, and an evaluation unit coupled to the driver and to the memory.

Abstract: A method is presented for calibrating a time-of-flight system having a time-of-flight sensor located behind a cover plate. The method involves emitting a plurality of sending pulses of light in response to respective trigger pulses of a control signal and detecting received pulses of light. Respective difference values are determined which are representative of a time period between one of the sending pulses and one of the received pulses. The difference values are accumulated into a number of bins of at least one histogram. The method further involves recording at least one crosstalk response in the histogram within a predetermined range of bins, and calibrating the histogram using the recorded crosstalk response. Finally, an output signal is generated which is indicative of a time-of-flight based on an evaluation of the calibrated histogram.

Abstract: A voltage converter comprises a first to a third capacitor (11-13), a supply terminal (16), a first and a second clock terminal (21, 22) and a transfer arrangement (15). A first electrode of the first capacitor (11) is connected to the first clock terminal (21) and a second electrode of the first capacitor (11) is connected to a first node (23) of the transfer arrangement (15). A first electrode of the second capacitor (12) is connected to the second clock terminal (22) and a second electrode of the second capacitor (12) is connected to a second node (24) of the transfer arrangement (15). A first electrode of the third capacitor (13) is permanently and directly connected to the second electrode of the first capacitor (11) and a second electrode of the third capacitor (13) is connected to a third node (25) of the transfer arrangement (15).

Abstract: A circuit for DC-DC conversion with current limitation comprises a DC-DC converter (100) with a coil (110) and a controllable switch (120) that can be switched into a low-impedance and a high-impedance state, and a current limiter (300a, 300b) for generating a control signal (IOC) for controlling the state of the controllable switch in the DC-DC converter (100). The current limiter (300a, 300b) is constructed such that the current (IL) through the coil at which the current limitation takes place is nearly independent of the ratio of the on-times and off-times of the controllable switch in the DC-DC converter (100).

Abstract: An optical sensor arrangement (10) comprises a light sensor (11) that is connected to a summation node (13) and is designed for generating a sensor current (S2), a current source (S2) connected to the summation node (13) and designed to provide a source current (S3), and an integrator (21) that is coupled to the summation node (13) and is designed for generating a first value (VP1) of an integrator signal (S6) by integrating during a first phase (P1) and for generating a second value (VP2) of the integrator signal (S6) by integrating during a second phase (P2). The optical sensor arrangement (10) comprises a sum and hold circuit (31) that is coupled to the integrator (21) and is designed to generate an analog output signal (S7) as a function of a difference of the first value (VP1) and the second value (VP2) of the integrator signal (S6).

Abstract: An optical sensor arrangement (10) comprises a light sensor (11) that is connected to a summation node (13) and is designed for generating a sensor current (S2), a current source (S2) connected to the summation node (13) and designed to provide a source current (S3), and an integrator (21) that is coupled to the summation node (13) and is designed for generating a first value (VP1) of an integrator signal (S6) by integrating during a first phase (P1) and for generating a second value (VP2) of the integrator signal (S6) by integrating during a second phase (P2). The optical sensor arrangement (10) comprises a sum and hold circuit (31) that is coupled to the integrator (21) and is designed to generate an analog output signal (S7) as a function of a difference of the first value (VP1) and the second value (VP2) of the integrator signal (S6).

Abstract: A circuit for DC-DC conversion with current limitation comprises a DC-DC converter (100) with a coil (110) and a controllable switch (120) that can be switched into a low-impedance and a high-impedance state, and a current limiter (300a, 300b) for generating a control signal (IOC) for controlling the state of the controllable switch in the DC-DC converter (100). The current limiter (300a, 300b) is constructed such that the current (IL) through the coil at which the current limitation takes place is nearly independent of the ratio of the on-times and off-times of the controllable switch in the DC-DC converter (100).

Abstract: A circuit arrangement (1) for voltage conversion comprises a forward branch (60) with a first load terminal (45) to which an electrical load (47) can be coupled and a feedback branch (61) with a sampling device (30). The electrical load (47) can be operated with pulse width modulation. A method for voltage conversion comprises the following steps: an electrical load (47) is supplied with energy using pulse width modulation. A feedback voltage (Vfb) that can be tapped at a terminal of the electrical load (47) is sampled in a first clock phase during which the electrical load (47) is supplied with energy. The voltage conversion is controlled as a function of the feedback voltage (Vfb).

Abstract: A circuit arrangement for supplying energy, comprising: a first input adapted to receive a first voltage from a first terminal of a control component, a second input adapted to receive a second voltage from a second terminal of the control component, a first output adapted to receive output a control signal to a control terminal of the control component for controlling an energy supply of an electrical load; and a power determining arrangement, comprising a switched-capacitor arrangement having an input coupled to the first and the second input of the circuit arrangement and an output coupled to the first output of the circuit arrangement.

Abstract: A circuit arrangement for supplying energy, comprising: a first input adapted to receive a first voltage from a first terminal of a control component, a second input adapted to receive a second voltage from a second terminal of the control component, a first output adapted to receive output a control signal to a control terminal of the control component for controlling an energy supply of an electrical load; and a power determining arrangement, comprising a switched-capacitor arrangement having an input coupled to the first and the second input of the circuit arrangement and an output coupled to the first output of the circuit arrangement.

Abstract: A circuit arrangement (10) comprises a circuit terminal (11) for supplying a data signal (DATA) having digital information, a logic circuit (12) that is coupled at an input (22) to the circuit terminal (11) for supplying the digital information, an activation circuit (13), and a voltage regulator (14) that is coupled for activation to an output (18) of the activation circuit (13). The activation circuit (13) comprises an input (16) that is coupled to the circuit terminal (11), a delay element (17) that is coupled to the input (16) of the activation circuit (13), and the output (18), connected to the delay element (17), for emitting an activation signal (SON).

Abstract: A circuit arrangement (10) comprises a circuit terminal (11) for supplying a data signal (DATA) having digital information, a logic circuit (12) that is coupled at an input (22) to the circuit terminal (11) for supplying the digital information, an activation circuit (13), and a voltage regulator (14) that is coupled for activation to an output (18) of the activation circuit (13). The activation circuit (13) comprises an input (16) that is coupled to the circuit terminal (11), a delay element (17) that is coupled to the input (16) of the activation circuit (13), and the output (18), connected to the delay element (17), for emitting an activation signal (SON).

Abstract: An integrated circuit includes a comparator having a first input, a second input, and an output for providing a comparison result. The first input is connected to a readable component having a predefined value, and the second input is connected to a reference component. A control unit is at the output of the comparator. The control unit controls at least one function block based on the comparison result.