Abstract: A method of manufacture of an integrated MOS semiconductor array for the low-frequency range having MOS components and circuit paths arranged on a semiconductor substrate. Exposed surfaces between the circuit paths are made hydrophobic by germinating with hexamethyl disilazane ((CH.sub.3).sub.3 SiNHSi(CH.sub.3).sub.3), so that the occurrence of leakage currents is avoided. In addition, in an integrated MOS semiconductor array in which the MOS components and the circuit path are covered with a protective layer, the surface of this protective layer is made hydrophobic. As a result, both leakage currents and parasitic capacitances are prevented.

Abstract: The invention relates to a protective arrangement for field-effect transistors with an insulated gate electrode. An integrated, indiffused protective diode whose breakdown voltage is smaller than that of the gate insulating layer is used therefor. The gist of the invention is that the breakdown voltage of the protective diode is set by two implantation processes, one of which is substantially limited to the region containing the in-diffused diode and the other of which substantially covers the surface of the substrate other than at least the channel region of the field-effect transistor so as to simultaneously increase the field inversion voltage.