Abstract: A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body and having body regions of a first conductivity type, a drift region of a second conductivity type that is opposite from the first conductivity type and is disposed between the body regions and a second surface of the semiconductor body that is opposite from the first surface, and an emitter layer of the second conductivity type that is disposed between the drift region and a second surface of the semiconductor body, the emitter layer having a higher dopant concentration than the drift region, a metal drain electrode directly adjoining the emitter layer. The metal drain electrode comprises spikes extending into the emitter layer.

Abstract: An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device (1) and a second transistor device (1a); a first biasing circuit (3) connected in parallel with a load path of the first transistor device (1) and comprising a first electronic switch (31); a second biasing circuit (3a) connected in parallel with a load path of the second transistor device (1a) and comprising a second electronic switch (31a); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device (1) and the second electronic switch (31a) based on the first half-bridge input signal (Sin), and drive the second transistor device (1a) and the first electronic switch (31) based on the second half-bridge input signal (Sina).

Abstract: A MOSFET includes a semiconductor body having a first side, a drift region, a body region forming a first pn-junction with the drift region, a source region forming a second pn-junction with the body region, in a vertical cross-section, a dielectric structure on the first side and having an upper side; a first gate electrode, a second gate electrode, a contact trench between the first and second gate electrodes, extending through the dielectric structure to the source region, in a horizontal direction a width of the contact trench has, in a first plane, a first value, and, in a second plane, a second value which is at most about 2.5 times the first value, and a first contact structure arranged on the dielectric structure having a through contact portion arranged in the contact trench, and in Ohmic contact with the source region.

Abstract: In an embodiment, a method of fabricating a superjunction semiconductor device includes implanting first ions into a first region of a first epitaxial layer using a first implanting apparatus and nominal implant conditions to produce a first region in the first epitaxial layer comprising the first ions and a first implant characteristic and implanting second ions into a second region of the first epitaxial layer, the second region being laterally spaced apart from the first region, using second nominal implanting conditions estimated to produce a second region in the first epitaxial layer having the second ions and a second implant characteristic that lies within an acceptable maximum difference of the first implant characteristic.

Abstract: A MOSFET includes a semiconductor body having a first side, a drift region, a body region forming a first pn-junction with the drift region, a source region forming a second pn-junction with the body region, in a vertical cross-section, a dielectric structure on the first side and having an upper side; a first gate electrode, a second gate electrode, a contact trench between the first and second gate electrodes, extending through the dielectric structure to the source region, in a horizontal direction a width of the contact trench has, in a first plane, a first value, and, in a second plane, a second value which is at most about 2.5 times the first value, and a first contact structure arranged on the dielectric structure having a through contact portion arranged in the contact trench, and in Ohmic contact with the source region.

Abstract: A method for manufacturing a MOSFET semiconductor device includes providing a wafer including a semiconductor body having a first side, a first semiconductor region adjacent to the first side, a second semiconductor region adjacent to the first side and forming a first pn-junction with the first semiconductor region, and a third semiconductor region adjacent to the first side and forming a second pn-junction with the second semiconductor region, a first dielectric layer arranged on the first side, a gate electrode embedded in the first dielectric layer, and a second dielectric layer arranged on the first dielectric layer. Next to the gate electrode, a trench is formed through the first dielectric layer and the second dielectric layer. At a side wall of the trench, a dielectric spacer is formed. The trench is extended into the semiconductor body to form a contact trench.

Abstract: A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body and having body regions of a first conductivity type, a drift region of a second conductivity type that is opposite from the first conductivity type and is disposed between the body regions and a second surface of the semiconductor body that is opposite from the first surface, and an emitter layer of the second conductivity type that is disposed between the drift region and a second surface of the semiconductor body, the emitter layer having a higher dopant concentration than the drift region, a metal drain electrode directly adjoining the emitter layer. The metal drain electrode comprises spikes extending into the emitter layer.

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: transistor cells formed along a first surface at a front side of a semiconductor portion; a drain structure between the transistor cells and a second surface of the semiconductor portion opposite to the first surface, the drain structure forming first pn junctions with body regions of the transistor cells and including an emitter layer directly adjoining the second surface; and a metal drain electrode directly adjoining the emitter layer. An integrated concentration of activated dopants along a shortest line between the metal drain electrode and a closest doped region of a charge type of the body regions is at most 1.5E13 cm?2. Further semiconductor device embodiments are described.

Abstract: Disclosed is a method. The method includes implanting recombination center particles into a semiconductor body via at least one contact hole in an insulation layer formed on top of the semiconductor body, forming a contact electrode electrically connected to the semiconductor body in the at least one contact hole, and annealing the semiconductor body to diffuse the recombination center particles in the semiconductor body. Forming the contact electrode includes forming a barrier layer on sections of the semiconductor body uncovered in the at least one contact hole, wherein the barrier layer is configured to inhibit the recombination center particles from diffusing out of the semiconductor body.

Abstract: A method for manufacturing a MOSFET semiconductor device includes providing a wafer including a semiconductor body having a first side, a first semiconductor region adjacent to the first side, a second semiconductor region adjacent to the first side and forming a first pn-junction with the first semiconductor region, and a third semiconductor region adjacent to the first side and forming a second pn-junction with the second semiconductor region, a first dielectric layer arranged on the first side, a gate electrode embedded in the first dielectric layer, and a second dielectric layer arranged on the first dielectric layer. Next to the gate electrode, a trench is formed through the first dielectric layer and the second dielectric layer. At a side wall of the trench, a dielectric spacer is formed. The trench is extended into the semiconductor body to form a contact trench.

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: transistor cells formed along a first surface at a front side of a semiconductor portion; a drain structure between the transistor cells and a second surface of the semiconductor portion opposite to the first surface, the drain structure forming first pn junctions with body regions of the transistor cells and including an emitter layer directly adjoining the second surface; and a metal drain electrode directly adjoining the emitter layer. An integrated concentration of activated dopants along a shortest line between the metal drain electrode and a closest doped region of a charge type of the body regions is at most 1.5E13 cm?2. Further semiconductor device embodiments are described.

Abstract: In an embodiment, a method of fabricating a superjunction semiconductor device includes implanting first ions into a first region of a first epitaxial layer using a first implanting apparatus and nominal implant conditions to produce a first region in the first epitaxial layer comprising the first ions and a first implant characteristic and implanting second ions into a second region of the first epitaxial layer, the second region being laterally spaced apart from the first region, using second nominal implanting conditions estimated to produce a second region in the first epitaxial layer having the second ions and a second implant characteristic that lies within an acceptable maximum difference of the first implant characteristic.

Abstract: An epitaxial layer is formed by epitaxy on a base substrate at a front side. From opposite to the front side, at least a portion of the base substrate is removed, wherein the base substrate is completely removed or a remnant base section has a thickness of at most 20 ?m. Dopants of a first charge type are implanted from opposite of the front side into an implant layer of the epitaxial layer. A metal drain electrode is formed opposite to the front side. At least the implant layer is heated to a temperature not higher than 500° C. The heating activates only a portion of the implanted dopants in the implant layer. After heating, an integrated concentration of activated dopants along a shortest line between the metal drain electrode and a closest doped region of a second, complementary charge type is at most 1.5E13 cm?2.

Abstract: Disclosed is a method. The method includes implanting recombination center particles into a semiconductor body via at least one contact hole in an insulation layer formed on top of the semiconductor body, forming a contact electrode electrically connected to the semiconductor body in the at least one contact hole, and annealing the semiconductor body to diffuse the recombination center particles in the semiconductor body. Forming the contact electrode includes forming a barrier layer on sections of the semiconductor body uncovered in the at least one contact hole, wherein the barrier layer is configured to inhibit the recombination center particles from diffusing out of the semiconductor body.

Abstract: An epitaxial layer is formed by epitaxy on a base substrate at a front side. From opposite to the front side, at least a portion of the base substrate is removed, wherein the base substrate is completely removed or a remnant base section has a thickness of at most 20 ?m. Dopants of a first charge type are implanted from opposite of the front side into an implant layer of the epitaxial layer. A metal drain electrode is formed opposite to the front side. At least the implant layer is heated to a temperature not higher than 500° C. The heating activates only a portion of the implanted dopants in the implant layer. After heating, an integrated concentration of activated dopants along a shortest line between the metal drain electrode and a closest doped region of a second, complementary charge type is at most 1.5E13 cm?2.

Abstract: The fabrication of a semiconductor component having a semiconductor body in which is arranged a very thin dielectric layer having sections which run in the vertical direction and which extend very deeply into the semiconductor body is disclosed. In one method a trench is formed in a drift zone region proceeding from the front side of a semiconductor body, a sacrificial layer is produced on at least a portion of the sidewalls of the trench and at least a portion of the trench is filled with a semiconductor material which is chosen such that the quotient of the net dopant charge of the semiconductor material in the trench and the total area of the sacrificial layer on the sidewalls of the trench between the semiconductor material and the drift zone region is less than the breakdown charge of the semiconductor material, and the sacrificial layer is replaced with a dielectric.

Abstract: The fabrication of a semiconductor component having a semiconductor body in which is arranged a very thin dielectric layer having sections which run in the vertical direction and which extend very deeply into the semiconductor body is disclosed. In one method a trench is formed in a drift zone region proceeding from the front side of a semiconductor body, a sacrificial layer is produced on at least a portion of the sidewalls of the trench and at least a portion of the trench is filled with a semiconductor material which is chosen such that the quotient of the net dopant charge of the semiconductor material in the trench and the total area of the sacrificial layer on the sidewalls of the trench between the semiconductor material and the drift zone region is less than the breakdown charge of the semiconductor material, and the sacrificial layer is replaced with a dielectric.