Abstract: An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.

Abstract: An integrated device comprises a functional circuit, a test circuit for testing the functional circuit and for providing an error data item and a register element for storing the error data item and for outputting the error data item at an error data output of the integrated device responsive to an output signal. The register element is connected to a data input of the integrated device in order to accept a data item, which is applied to the data input, responsive to the output signal.

Abstract: A device can be used for refreshing memory contents of first and second memory cells. The memory contents of the first memory cells are refreshed in a first period of time and the memory contents of the second memory cells are refreshed in a second period of time. A pre-charge circuit is provided for bit lines for the first memory cells and the second memory cells. A controller may be coupled to the pre-charge circuit to control the pre-charge circuit such that a pre-charge voltage may be applied to the bit lines of the first memory cells during the first period of time and not during the second period of time and that the pre-charge voltage may be applied to the bit lines of the second memory cells during the second period of time and not during the first period of time.

Abstract: A method for improving the reliability of a memory having a used memory region and an unused memory region, wherein defect memory elements in the used memory region can be substituted by functional memory elements in the unused memory region, having the steps of providing the used memory region with a first stress sequence; and providing the unused memory region with a second stress sequence.

Abstract: A memory device and method for internal voltage monitoring is disclosed. One embodiment includes at least one error register configured to store a particular error flag during the stress test. This error flag is generated if the supply voltage applied at the memory device during the test method in the memory device or an internally generated voltage of the memory device lies below a predetermined threshold value.

Abstract: An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.

Abstract: A semiconductor memory and method for testing semiconductor memory is disclosed. One embodiment provides a method including activating a first master word line. An electric voltage difference between the first master word line and an adjacent master word line is generated. The leakage current between the first master word line and the adjacent master word line is measured.

Abstract: A device is disclosed for refreshing memory contents of first and second memory cells, wherein the memory contents of the first memory cells are refreshed in a first period of time and the memory contents of the second memory cells are refreshed in a second period of time, having a pre-charge circuit for bit lines for the first memory cells and the second memory cells, and having a controller which may be coupled to the pre-charge circuit to control the pre-charge circuit such that a pre-charge voltage may be applied to the bit lines of the first memory cells during the first period of time and not during the second period of time and that the pre-charge voltage may be applied to the bit lines of the second memory cells during the second period of time and not during the first period of time.

Abstract: Methods and apparatus for applying a test pattern to cells in a memory module. A test auxiliary device in a memory module contains a test pattern selection device for selecting a test pattern from at least two elementary M-bit test patterns. The test pattern is applied to a group of M data lines of the memory module, M being an integer.

Abstract: A memory circuit comprises a memory cell array with dynamic memory cells arranged on word lines and bit lines, a selection unit providing selection information and a refresh circuit selecting the memory cells in each case in dependence on the selection information and refreshing the selected memory cells so that any information stored therein is retained in each case.

Abstract: An integrated semiconductor memory with a test function comprises a bit line pair having a first end and a second end. A voltage generation circuit having a first connection and a second connection is coupled to the first end of the bit line pair. A plurality of memory cells are connected to a bit line of the bit line pair between the first end and second end of the bit line pair. A controllable switch is connected between the second end of the bit line pair.

Abstract: An integrated device comprises a functional circuit, a test circuit for testing the functional circuit and for providing an error data item and a register element for storing the error data item and for outputting the error data item at an error data output of the integrated device responsive to an output signal. The register element is connected to a data input of the integrated device in order to accept a data item, which is applied to the data input, responsive to the output signal.

Abstract: A semiconductor memory and a method for operating the latter in order are provided, at least in testwise fashion, to deactivate a word line segment (12) of a segmented word line not via a first line (21) otherwise used for deactivation, but rather via a second line (22) via that the word line segment (12) is otherwise activated. The second line (22) can optionally be biased with a second potential (Vpp) provided for activation or with a third potential (Vgnd). If the third potential (Vgnd) is used for at least temporarily deactivating the word line segment (12), the word line segment can be driven via a switching element (17), which couples the word line segment to the second line (22), without the complementary switching element (16) of the driver segment (20) having to be used for deactivation.

Abstract: A method for improving the reliability of a memory having a used memory region and an unused memory region, wherein defect memory elements in the used memory region can be substituted by functional memory elements in the unused memory region, having the steps of providing the used memory region with a first stress sequence; and providing the unused memory region with a second stress sequence.

Abstract: A semiconductor memory and a test method for testing whether word line segments (12) are floating after an activation operation or a deactivation operation is disclosed. For this purpose, the charge-reversal current (I) that occurs in the event of a word line segment (12) being subjected to charge reversal or a charge quantity (Q) which is fed to the word line (12) or conducted away from the word line segment (12) as a result of this is measured. If, upon activation or deactivation of a word line segment (12), the measured charge-reversal current (I) or the corresponding charge quantity (Q) is less than a lower limit value, it is ascertained that the relevant word line segment (12) has a defective contact terminal. In this way, high-impedance or defective contact hole fillings can thereby be identified and the associated word line segments (12) can be replaced by redundant word lines.

Abstract: A method for operating a semiconductor memory and to a semiconductor memory with at least one sense amplifier and device for switching the sense amplifier to or off at least one line is disclosed. The means is, during the switching of the sense amplifier to the line, placed in a conductive state for a differently long time and/or differently strongly, depending on the respective operating mode of the semiconductor memory.

Abstract: A method for detecting a leakage current in a bit line of a semiconductor memory is disclosed. In one embodiment, the method includes isolating the connection of a sense amplifier from a bit line via an isolation transistor, reading out a memory cell to the bit line, waiting until a predetermined delay time has elapsed, so that a leakage current measurably changes the voltage on the bit line within the delay time. The sense amplifier is short circuited with the bit line via the isolation transistor. The voltage on the bit line is collected by the sense amplifier, and compared with a reference voltage so as to detect the leakage current.

Abstract: A semiconductor memory includes storage cells (2) that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (V1, V2) in order to open and close the transistor. The electrode potential (V2) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory (1) so that the second electrical potential (V2) becomes more different from the first electrical potential (V1) as the temperature (T) increases.

Abstract: The invention relates to a RAM store having a shared SA structure, in which sense amplifiers (SA) arranged in SA strips (10) between two respective adjacent cell blocks are used by a plurality of bit line pairs (21, 22; 21–24) from the adjacent cell blocks and the bit line pairs (21, 22; 21–24) have respective charge equalization circuits individually associated with them for the purpose of performing charge equalization between the bit line halves of the bit line pairs (21, 22; 21–24) in a precharge phase, where a shorting transistor (30) is provided which, when prompted by a control signal (EQLx), connects the bit line halves (BLT, BLC) of the bit line pairs (21, 22; 21–24) which are in the precharge phase to one another.

Abstract: A semiconductor circuit comprises a fuse and a photoelement. A conduction layer of the fuse at least partly shades a photosensor region of the photoelement from a light bundle falling onto the semiconductor circuit. An arrangement for electro-optical monitoring of fuses of a semiconductor circuit additionally comprises an illumination device for generating the light bundle and a measuring device connected to two of the terminal contacts of the semiconductor circuit. In a method for the electro-optical monitoring of fuses of a semiconductor circuit a measuring device is connected to two of the terminal contacts and the semiconductor circuit is illuminated with a light bundle.