Abstract: A voltage controlled oscillator arrangement is disclosed. The arrangement includes a voltage controlled oscillator and a quadratic extension component. The voltage controlled oscillator has a tuning port. The tuning port is configured to select an operating frequency according to an applied voltage. The quadratic extension component is configured to generate a quadratic tuning voltage that as the applied voltage to the tuning port. The quadratic tuning voltage is generated according to a linear temperature compensation signal.

Abstract: A voltage controlled oscillator arrangement is disclosed. The arrangement includes a voltage controlled oscillator and a quadratic extension component. The voltage controlled oscillator has a tuning port. The tuning port is configured to select an operating frequency according to an applied voltage. The quadratic extension component is configured to generate a quadratic tuning voltage that as the applied voltage to the tuning port. The quadratic tuning voltage is generated according to a linear temperature compensation signal.

Abstract: A fast frequency-hopping transceiver comprises a RF-unit arranged on a first chip, a base-band unit on a second chip, a bidirectional operable data and control interface arranged between said first and said second chip having at least one data line for data communication, at least one control line for controlling the data communication and at least one clock line for providing a clock signal, memory means implemented within said RF-unit containing all the required chip settings which are specific to a certain frequency of received and/or transmitted data being part of the intended hopping sequence. The transceiver also includes control means for programming said memory means during an initialization phase during a set-up of a communication link of said data communication.

Abstract: A fast frequency-hopping transceiver comprises a RF-unit arranged on a first chip, a base-band unit on a second chip, a bidirectional operable data and control interface arranged between said first and said second chip having at least one data line for data communication, at least one control line for controlling the data communication and at least one clock line for providing a clock signal, memory means implemented within said RF-unit containing all the required chip settings which are specific to a certain frequency of received and/or transmitted data being part of the intended hopping sequence. The transceiver also includes control means for programming said memory means during an initialization phase during a set-up of a communication link of said data communication.

Abstract: A fast frequency-hopping transceiver comprises a RF-unit arranged on a first chip, a base-band unit on a second chip, a bidirectional operable data and control interface arranged between said first and said second chip having at least one data line for data communication, at least one control line for controlling the data communication and at least one clock line for providing a clock signal, memory means implemented within said RF-unit containing all the required chip settings which are specific to a certain frequency of received and/or transmitted data being part of the intended hopping sequence. The transceiver also includes control means for programming said memory means during an initialization phase during a set-up of a communication link of said data communication.

Abstract: A DC-offset correction circuit includes an analog circuit to generate a plurality of analog offset-correction signal values, each of which are assigned to a hop band. The analog circuit is coupled to a tap of an analog receiver chain and includes a first analog selector to select an analog offset-correction signal value, the selected analog offset correcting signal value being assigned to a current hop band. Further, the DC-offset correction circuit includes a combiner to combine a received signal with the selected analog offset-correction signal value and feed the analog receiver chain.

Abstract: A DC-offset correction circuit includes an analog circuit to generate a plurality of analog offset-correction signal values, each of which are assigned to a hop band. The analog circuit is coupled to a tap of an analog receiver chain and includes a first analog selector to select an analog offset-correction signal value, the selected analog offset correcting signal value being assigned to a current hop band. Further, the DC-offset correction circuit includes a combiner to combine a received signal with the selected analog offset-correction signal value and feed the analog receiver chain.

Abstract: A calibration unit is designed to contain an oscillator circuit whose frequency is determined by the RC time constant of a resistor, which is of the same type as the resistor used in the filter circuit that is to be calibrated, and of a capacitor device which has been set to a fixed value. The oscillator frequency is converted into counting pulses, and the number of counting pulses which is counted in a modulo binary counter within a time interval is transmitted as a digital calibration signal for a calibratable capacitor device in the filter circuit in order to calibrate the latter.

Abstract: A fast frequency-hopping transceiver comprises a RF-unit arranged on a first chip, a base-band unit on a second chip, a bidirectional operable data and control interface arranged between said first and said second chip having at least one data line for data communication, at least one control line for controlling the data communication and at least one clock line for providing a clock signal, memory means implemented within said RF-unit containing all the required chip settings which are specific to a certain frequency of received and/or transmitted data being part of the intended hopping sequence. The transceiver also includes control means for programming said memory means during an initialization phase during a set-up of a communication link of said data communication.

Abstract: A calibration unit is designed to contain an oscillator circuit whose frequency is determined by the RC time constant of a resistor, which is of the same type as the resistor used in the filter circuit that is to be calibrated, and of a capacitor device which has been set to a fixed value. The oscillator frequency is converted into counting pulses, and the number of counting pulses which is counted in a modulo binary counter within a time interval is transmitted as a digital calibration signal for a calibratable capacitor device in the filter circuit in order to calibrate the latter.

Abstract: A circuit configuration for smoothing an input voltage includes two input terminals for receiving the input voltage. A negative-feedback amplifier has two inputs and an output. A capacitor is connected to one of the inputs of the amplifier. An output terminal is connected to the output of the amplifier. A converter element has a first terminal connected to one of the input terminals, a second terminal connected to the one input of the amplifier and to the capacitor, and a third terminal connected to the output of the amplifier.

Abstract: A current driver circuit with transverse current regulation includes a CMOS output driver stage. Each output transistor is assigned one gate-coupled and source-coupled current polling transistor. Control signals are derived from currents flowing through the current polling transistors, and a first branch of a differential amplifier is triggered by these signals. A second branch thereof is controlled by a reference signal. Input branches of current mirrors are each connected into an output circuit of the differential amplifier, and output branches of the current mirrors include gate-coupled and source-coupled transistors for the connection of an input signal. Center pickups of the output branches of these current mirrors each serve to trigger one of the output transistors. The current driver circuit has a high output voltage rise and output transistors with little surface area, and could be operated with a low supply voltage.