Patents by Inventor Manfred Reithinger

Manfred Reithinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiple chip semiconductor arrangement having electrical components in separating regions
    Patent number: 7060529
    Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: June 13, 2006
    Assignee: Infineon Technologies AG
    Inventors: Manfred Reithinger, Mike Killian, Gerd Frankowsky, Oliver Kiehl, Gerhard Mueller, Ernst Stahl, Hartmud Terletzki, Thomas Vogelsang
  • Multiple chip semiconductor arrangement having electrical components in separating regions
    Publication number: 20050001298
    Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.
    Type: Application
    Filed: May 7, 2004
    Publication date: January 6, 2005
    Inventors: Manfred Reithinger, Mike Killian, Gerd Frankowsky, Oliver Kiehl, Gerhard Mueller, Ernst Stahl, Hartmud Terletzki, Thomas Vogelsang
  • Multiple chip semiconductor arrangement having electrical components in separating regions
    Patent number: 6815803
    Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: November 9, 2004
    Assignee: Infineon Technologies AG
    Inventors: Manfred Reithinger, Mike Killian, Gerd Frankowsky, Oliver Kiehl, Gerhard Mueller, Ernst Stahl, Hartmud Terletzki, Thomas Vogelsang
  • Semiconductor package and method
    Patent number: 6730989
    Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: May 4, 2004
    Assignee: Infineon Technologies AG
    Inventors: Manfred Reithinger, Mike Killian, Gerd Frankowsky, Oliver Kiehl, Gerhard Mueller, Ernst Stahl, Hartmud Terletzki, Thomas Vogelsang