Abstract: A system comprises one or more slave elements operably coupled to a plurality of master devices. A central protection function is operably coupled to a first communication bus and configured to control data flow between the one or more slave elements and the plurality of master devices via the communication bus.

Abstract: An integrated circuit device comprising at least one memory interface module arranged to be operably coupled between at least one data storage device and a plurality of master devices within a data processing system. The at least one memory interface module comprises a plurality of buffers and at least one data access control module. The at least one data access control module being arranged to fetch data from the at least one data storage device in response to a received memory access request comprising a master device identifier, select at least one buffer based at least partly on the master device identifier of the received access request, and load the fetched data into the selected at least one buffer.

Abstract: A system comprises a first master element; and at least one shared communication element arranged to operably couple the first master element to at least one slave element. The system further comprises at least one validation element located on at least one further validation path located between the first master element and the at least one slave element, wherein the at least one validation element is arranged to validate at least one of: at least one access request by the first master element; and a response to an access request from the at least one slave element.

Abstract: A system comprises at least two random access memory (RAM) elements arranged to store data redundantly. The system further comprises RAM routing logic comprising comparison logic operably coupled to the at least two RAM elements and arranged to compare redundant data read from the at least two RAM elements, and check and validation logic, independent of the RAM routing logic, operably coupled to the at least two RAM elements and arranged to additionally detect an error in the redundant data read from the at least two RAM elements and provide an error indication signal to the RAM routing logic in response thereto. The RAM routing logic further comprises selection logic arranged to dynamically select redundant data from one of the at least two RAM elements based on the comparison of the redundant data and the error indication signal.

Abstract: A multi-node communications system is provided with communications protocol using both static (11, 12, 13, 18) (pre-determined) and dynamic (51, 52, 53 . . . ) (run-time determined) consecutive communication slots is used. The system has a number of distributed communication nodes, each node being arranged for communicating frames of data with the other nodes during both the static (11, 12, 13 . . . ) and the dynamic (51, 52, 53 . . . ) communication slots. Each node includes a synchronized time base 5 made up of consecutive timeslots (11, 12, 13 . . . , 51, 52, 53 . . . ). The timebase 5 has substantially the same error tolerance in each node. For static communication (10), a predetermined number of timeslots (20) are utilized for each static communication slot. For dynamic communication a dynamically allocated number of timeslots (60) are utilized for each dynamic communication slot. In this way both static and dynamic media arbitration is provided within a periodically recurring communication pattern.

Abstract: A system for distributing available memory resource comprising at least two random access memory (RAM) elements and RAM routing logic. The RAM routing logic comprises configuration logic to dynamically distribute the available memory resource into a first memory area providing redundant memory storage and a second memory area providing non-redundant memory storage.

Abstract: A system comprises at least two random access memory (RAM) elements arranged to store data redundantly. The system further comprises RAM routing logic comprising comparison logic operably coupled to the at least two RAM elements and arranged to compare redundant data read from the at least two RAM elements, and check and validation logic, independent of the RAM routing logic, operably coupled to the at least two RAM elements and arranged to additionally detect an error in the redundant data read from the at least two RAM elements and provide an error indication signal to the RAM routing logic in response thereto. The RAM routing logic further comprises selection logic arranged to dynamically select redundant data from one of the at least two RAM elements based on the comparison of the redundant data and the error indication signal.

Abstract: A system comprises a first master element; and at least one shared communication element arranged to operably couple the first master element to at least one slave element. The system further comprises at least one validation element located on at least one further validation path located between the first master element and the at least one slave element, wherein the at least one validation element is arranged to validate at least one of: at least one access request by the first master element; and a response to an access request from the at least one slave element.

Abstract: A system comprises one or more slave elements operably coupled to a plurality of master devices. A central protection function is operably coupled to a first communication bus and configured to control data flow between the one or more slave elements and the plurality of master devices via the communication bus.

Abstract: A multi-node communications system is provided with communications protocol using both static (11, 12, 13, 18) (pre-determined) and dynamic (51, 52, 53 . . . ) (run-time determined) consecutive communication slots is used. The system has a number of distributed communication nodes, each node being arranged for communicating frames of data with the other nodes during both the static (11, 12, 13 . . . ) and the dynamic (51, 52, 53 . . . ) communication slots. Each node includes a synchronized time base 5 made up of consecutive timeslots (11, 12, 13 . . . , 51, 52, 53 . . . ). The timebase 5 has substantially the same error tolerance in each node. For static communication (10), a predetermined number of timeslots (20) are utilized for each static communication slot. For dynamic communication a dynamically allocated number of timeslots (60) are utilized for each dynamic communication slot. In this way both static and dynamic media arbitration is provided within a periodically recurring communication pattern.

Abstract: An integrated circuit having a power transistor and a circuit arrangement functioning in a temperature dependant manner and thermally coupled to the power transitor. The integrated circuit is used to reliably disconnect the power transistor in the event of overheating., particularly in the case of inductive loads, and does not reactivate the power transistor until, for example, an edge change has occurred at the base terminal of the integrated circuit.