Patents by Inventor Manfred Walz
Manfred Walz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10838449Abstract: Automatic detection of clock grid misalignments and automatic realignment including loading a test pattern into a first storage element on a first clock grid on a circuit; scanning the test pattern from the first storage element on the first clock grid to a second storage element on a second clock grid on the circuit; reading the scanned test pattern from the second storage element on the second clock grid; evaluating the scanned test pattern for errors; and in response to detecting an error in the scanned test pattern, triggering an alignment of the first clock grid and the second clock grid.Type: GrantFiled: July 5, 2018Date of Patent: November 17, 2020Assignee: International Business Machines CorporationInventors: Benedikt Geukes, Matteo Michel, Manfred Walz
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Publication number: 20200012312Abstract: Automatic detection of clock grid misalignments and automatic realignment including loading a test pattern into a first storage element on a first clock grid on a circuit; scanning the test pattern from the first storage element on the first clock grid to a second storage element on a second clock grid on the circuit; reading the scanned test pattern from the second storage element on the second clock grid; evaluating the scanned test pattern for errors; and in response to detecting an error in the scanned test pattern, triggering an alignment of the first clock grid and the second clock grid.Type: ApplicationFiled: July 5, 2018Publication date: January 9, 2020Inventors: BENEDIKT GEUKES, MATTEO MICHEL, MANFRED WALZ
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Patent number: 10156610Abstract: A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.Type: GrantFiled: May 3, 2017Date of Patent: December 18, 2018Assignee: International Business Machines CorporationInventors: Benedikt Geukes, Manfred Walz, Matteo Michel
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Publication number: 20180321314Abstract: A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.Type: ApplicationFiled: May 3, 2017Publication date: November 8, 2018Inventors: Benedikt Geukes, Manfred Walz, Matteo Michel
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Publication number: 20180321315Abstract: A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.Type: ApplicationFiled: December 7, 2017Publication date: November 8, 2018Inventors: Benedikt Geukes, Manfred Walz, Matteo Michel
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Patent number: 9202060Abstract: The present invention relates to a method for a self-boot of an electronic device, wherein an external component is accessible through an interface of the electronic device (101), the method comprising, determining a boot mode for booting the electronic device, wherein the determined boot mode is defined as a secure boot mode; disabling the interface, thereby prohibiting access to the component through the interface, thereby defining a secure state of the electronic device; loading a first code comprising a sequence of executable instructions to be executed for booting the electronic device; loading a second code, the second code being encrypted; and decrypting the second code and executing the second code, thereby enabling the interface, and switching the electronic device from the secure state to a debugging state.Type: GrantFiled: December 6, 2012Date of Patent: December 1, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benedikt Geukes, Heiko Michel, Matteo Michel, Manfred Walz
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Patent number: 9110137Abstract: A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.Type: GrantFiled: December 3, 2013Date of Patent: August 18, 2015Assignee: International Business Machines CorporationInventors: Martin Doerr, Benedikt Geukes, Holger Horbach, Matteo Michel, Manfred Walz
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Patent number: 8984355Abstract: A technique for controlling scan access of multiple scan devices (including or more slave scan devices and a master scan device) to a scan chain includes sending, by a requesting slave scan device included in the one or more slave scan devices, a first request for access to the scan chain to the master scan device. The master scan device and the one or more slave scan devices are connected to the scan chain. The technique also includes receiving, at the requesting slave scan device, an evaluation result from the master scan device and accessing, by the requesting slave scan device, the scan chain in response to the evaluation result indicating access granted. Finally, the technique includes sending, by the requesting slave scan device, one or more second requests for access to the scan chain to the master scan device in response to the evaluation result indicating access denied.Type: GrantFiled: December 6, 2012Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: Benedikt Geukes, Heiko Michel, Matteo Michel, Manfred Walz
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Patent number: 8972808Abstract: A technique for controlling scan access of multiple scan devices (including or more slave scan devices and a master scan device) to a scan chain includes sending, by a requesting slave scan device included in the one or more slave scan devices, a first request for access to the scan chain to the master scan device. The master scan device and the one or more slave scan devices are connected to the scan chain. The technique also includes receiving, at the requesting slave scan device, an evaluation result from the master scan device and accessing, by the requesting slave scan device, the scan chain in response to the evaluation result indicating access granted. Finally, the technique includes sending, by the requesting slave scan device, one or more second requests for access to the scan chain to the master scan device in response to the evaluation result indicating access denied.Type: GrantFiled: March 26, 2013Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Benedikt Geukes, Heiko Michel, Matteo Michel, Manfred Walz
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Patent number: 8914693Abstract: A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.Type: GrantFiled: February 15, 2012Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Martin Doerr, Benedikt Geukes, Holger Horbach, Matteo Michel, Manfred Walz
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Publication number: 20140089749Abstract: A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.Type: ApplicationFiled: December 3, 2013Publication date: March 27, 2014Applicant: International Business Machines CorporationInventors: Martin Doerr, Benedikt Geukes, Holger Horbach, Matteo Michel, Manfred Walz
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Publication number: 20130212445Abstract: A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.Type: ApplicationFiled: February 15, 2012Publication date: August 15, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin Doerr, Benedikt Geukes, Holger Horbach, Matteo Michel, Manfred Walz
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Patent number: 8510072Abstract: Additional circuitry is included in an input cell design structure for an integrated circuit to detect and report transitions on an input that was expected to be stable, and to store that event for later analysis. Two or more modified input cells may have their error indications daisy-chained together to minimize additional routing. The storage elements may be included in a scan chain to allow for isolation of which input had the unexpected transition.Type: GrantFiled: November 12, 2010Date of Patent: August 13, 2013Assignee: International Business Machines CorporationInventors: Thomas Buechner, Martin Eckert, Matthias Klein, Manfred Walz, Andreas Wagner, Gerhard Zilles
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Patent number: 8359503Abstract: Methods and corresponding test systems for generating a chip facility waveform from a series of chip snapshots. The methods including, (i) testing an integrated chip multiple times, each time increasing a clockstop delay delaying a clockstop generated by triggered error condition each time determining the state of state holding elements of the integrated circuit and (ii) testing an integrated circuit chip one time to generate a error condition and determining multiple times the states of state holding elements of the integrated circuit based on previous states of the state holding elements.Type: GrantFiled: September 16, 2008Date of Patent: January 22, 2013Assignee: International Business Machines CorporationInventors: Rolf Fritz, Andreas Koenig, Christopher Smith, Manfred Walz
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Publication number: 20120123724Abstract: Additional circuitry is included in an input cell design structure for an integrated circuit to detect and report transitions on an input that was expected to be stable, and to store that event for later analysis. Two or more modified input cells may have their error indications daisy-chained together to minimize additional routing. The storage elements may be included in a scan chain to allow for isolation of which input had the unexpected transition.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Applicant: International Business Machines CorporationInventors: Thomas Buechner, Martin Eckert, Matthias Klein, Andreas Wagner, Manfred Walz, Gerhard Zilles
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Publication number: 20100070232Abstract: Methods and corresponding test systems for generating a chip facility waveform from a series of chip snapshots. The methods including, (i) testing an integrated chip multiple times, each time increasing a clockstop delay delaying a clockstop generated by triggered error condition each time determining the state of state holding elements of the integrated circuit and (ii) testing an integrated circuit chip one time to generate a error condition and determining multiple times the states of state holding elements of the integrated circuit based on previous states of the state holding elements.Type: ApplicationFiled: September 16, 2008Publication date: March 18, 2010Inventors: Rolf Fritz, Andreas Koenig, Christopher Smith, Manfred Walz
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Patent number: 5388240Abstract: A data mechanism having a random access memory (RAM) which has a plurality of groups of memory chips, each group being divisible into two equally sized chip sets. Each group of memory chips is addressed by a first address and each individual memory chip is addressed by a second address. The random access memory contains stored data. A cache, connected to the RAM, stores a portion of data stored in the RAM and is accessed by a cache address for separately reading requested data therefrom. The cache provides a cache miss signal when it does not contain the requested data. A CPU, connected to the cache and the RAM, receives the cache miss signal and provides responsive thereto, a starting address to the random access memory for starting a block transfer from the random access memory to the cache in two shots. The starting address includes the first address and the second address.Type: GrantFiled: August 29, 1991Date of Patent: February 7, 1995Assignee: International Business Machines CorporationInventors: Ulrich Olderdissen, Manfred Walz