Abstract: A method and apparatus for frame decoding, in a system which has a series bit data flow with a frame structure including a periodically occurring item of synchronizing information which characterizes the start of each frame, uses a synchronizing bit as synchronizing information. A logic AND-link is perfomed, with data in successive search frames until only one bit, the synchronizing bit, in the search frame is set at logic "1" and this setting is retained for a plurality of search frames. A synchronizing signal, corresponding to the time position of the synchronizing bit, is generated and the bit flow and/or the synchronizing signal are delayed so that the synchronizing signal occurs in synchronism with a delayed bit flow.