Patents by Inventor Manfred Zupke

Manfred Zupke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11616590
    Abstract: A system (100) comprising: a first unit (104) and one or more second units (104). The first unit (102) comprises: a timing reference (114) configured to provide a master-timing-reference-signal; a master time block configured to provide a master-time-signal (117) for the first unit (102) based on the master-timing-reference-signal; and a first interface (122) configured to: receive timestamped-processed-second-RF-signals from the one or more second units (104); and provide a first-unit-timing-signal (262) to the one or more second units (104) based on the master-time-signal.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: March 28, 2023
    Assignee: NXP B.V.
    Inventors: Martin Klein, Martin Kessel, Sebastian Bohn, Manfred Zupke, Evert-Jan Pol, Hendrik van der Ploeg, Andreas Johannes Gerrits, Prince Thomas
  • Patent number: 11522557
    Abstract: A digital conversion system including a sigma-delta converter, a tone generator that generates injects a tone signal into the conversion path of the sigma-delta converter at a frequency that is outside operating signal frequency range, a tone detector that isolates and detects a level of the injected tone signal and provides a corresponding tone level value, a tone ratio comparator that converts the tone level value into a tone level ratio and that compares the converted tone level ratio with an expected tone level ratio to provide an error signal, and a loop controller that converts the error signal to a correction signal to adjust a loop filter frequency the sigma-delta converter. Tones may be serially injected one at a time or simultaneously in parallel for determining a measured tone level ratio for comparison with a corresponding one of multiple stored expected tone level ratios.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: December 6, 2022
    Assignee: NXP B.V.
    Inventors: Robert Rutten, Martin Kessel, Hendrik van der Ploeg, Lucien Johannes Breems, Muhammed Bolatkale, Evert-Jan Pol, Manfred Zupke, Bernard Burdiek, Johannes Hubertus Antonius Brekelmans, Shagun Bajoria
  • Patent number: 11502699
    Abstract: A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: November 15, 2022
    Assignee: NXP B.V.
    Inventors: Robert Rutten, Hendrik van der Ploeg, Lucien Johannes Breems, Martin Kessel, Muhammed Bolatkale, Bernard Burdiek, Manfred Zupke, Johannes Hubertus Antonius Brekelmans, Shagun Bajoria
  • Publication number: 20220200718
    Abstract: A system (100) comprising: a first unit (104) and one or more second units (104). The first unit (102) comprises: a timing reference (114) configured to provide a master-timing-reference-signal; a master time block configured to provide a master-time-signal (117) for the first unit (102) based on the master-timing-reference-signal; and a first interface (122) configured to: receive timestamped-processed-second-RF-signals from the one or more second units (104); and provide a first-unit-timing-signal (262) to the one or more second units (104) based on the master-time-signal.
    Type: Application
    Filed: December 7, 2021
    Publication date: June 23, 2022
    Inventors: Martin Klein, Martin Kessel, Sebastian Bohn, Manfred Zupke, Evert-Jan Pol, Hendrik van der Ploeg, Andreas Johannes Gerrits, Prince Thomas
  • Patent number: 10541699
    Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: January 21, 2020
    Assignee: NXP B.V.
    Inventors: Robert Rutten, Massimo Ciacci, Manfred Zupke, Lucien Johannes Breems, Johannes Hubertus Antonius Brekelmans, Muhammed Bolatkale, Shagun Bajoria, Soheil Bahrami
  • Patent number: 7259799
    Abstract: Disclosed is an AGC detector device and an AGC detecting method for television receivers displaying video pictures consisting of a plurality of horizontal lines to be built up successively, wherein a CVBS signal is inputted which includes horizontal sync pulses having a front porch region and a back porch region and occurring once a horizontal line during a horizontal sync period when generating a current video picture, and further includes vertical sync pulses occurring during a vertical sync period before the generation of a new video picture and including serration pulses which occur during a serration pulse region being part of the vertical sync period. Further, gating pulses are generated having a period which is equal to the line period of the horizontal sync pulses. Said gating pulses are adjusted such that they occur at the back porch region of the horizontal sync pulses.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: August 21, 2007
    Assignee: NXP B.V.
    Inventors: Hans-Jürgen Kühn, Manfred Zupke
  • Patent number: 7071773
    Abstract: The invention relates to a digital phase locked loop (PLL) 12 for demodulating an intermediate frequency signal. The digital phase locked loop 12 comprises two coordinate rotation digital computers 24 and 30 in its phase detector. The robustness the PLL 12 can be improved by means of a gain control circuit 27, a sign detector 20, a carrier monitoring circuit 28 and an adjustable loop filter 32.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: July 4, 2006
    Assignee: Koninklijke Philips Electronics, N.V.
    Inventors: Hans-Jürgen Kühn, Manfred Zupke
  • Publication number: 20060017498
    Abstract: The invention relates to a digital phase locked loop (PLL) 12 for demodulating an intermediate frequency signal. The digital phase locked loop 12 comprises two coordinate rotation digital computers 24 and 30 in its phase detector. The robustness of the PLL 12 can be improved by means of a gain control circuit 27, a sign detector 20, a carrier monitoring circuit 28 and an adjustable loop filter 32.
    Type: Application
    Filed: February 3, 2003
    Publication date: January 26, 2006
    Applicant: Koninklijke Philips Electronics N.V.
    Inventors: Hans-Jurgen Kuhn, Manfred Zupke
  • Publication number: 20050088367
    Abstract: Disclosed is an AGC detector device and an AGC detecting method for television receivers displaying video pictures consisting of a plurality of horizontal lines to be built up successively, wherein a CVBS signal is inputted which includes horizontal sync pulses having a front porch region and a back porch region and occurring once a horizontal line during a horizontal sync period when generating a current video picture, and further includes vertical sync pulses occurring during a vertical sync period before the generation of a new video picture and including serration pulses which occur during a serration pulse region being part of the vertical sync period. Further, gating pulses are generated having a period which is equal to the line period of the horizontal sync pulses. Said gating pulses are adjusted such that they occur at the back porch region of the horizontal sync pulses.
    Type: Application
    Filed: February 3, 2003
    Publication date: April 28, 2005
    Inventors: Hans-Jurgen Kuhn, Manfred Zupke