Patents by Inventor Mangesh Bangar
Mangesh Bangar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11650506Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.Type: GrantFiled: October 11, 2019Date of Patent: May 16, 2023Assignee: Applied Materials Inc.Inventors: Huixiong Dai, Mangesh Bangar, Christopher S. Ngai, Srinivas D. Nemani, Ellie Y. Yieh, Steven Hiloong Welch
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Publication number: 20200233307Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.Type: ApplicationFiled: October 11, 2019Publication date: July 23, 2020Inventors: Huixiong DAI, Mangesh BANGAR, Christopher S. NGAI, Srinivas D. NEMANI, Ellie Y. YIEH, Steven Hiloong WELCH
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Patent number: 10429747Abstract: Embodiments disclosed herein relate to methods and systems for correcting overlay errors on a surface of a substrate. A processor performs a measurement process on a substrate to obtain an overlay error map. The processor determines an order of treatment for the substrate based on the overlay error map. The order of treatment includes one or more treatment processes. The processor generates a process recipe for a treatment process of the one or more treatment processes in the order of treatment. The processor provides the process recipe to a substrate treatment apparatus.Type: GrantFiled: November 13, 2017Date of Patent: October 1, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Mangesh Bangar, Srinivas D. Nemani, Steve G. Ghanayem, Ellie Y. Yieh
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Publication number: 20190094179Abstract: Aspects disclosed herein relate to methods of high-volume manufacturing of an array of biological sensing devices on a substrate, each of the biological sensing devices having a vertical or horizontal membrane having one or more solid-state nanopores therethrough, and methods for simple fluidic addressing of each nanopore. In one aspect, a method for forming a nanopore by applying a voltage from a positive electrode to a negative electrode through a free-standing membrane is disclosed. In other aspects, methods for forming a plurality of nanopores on a wafer are disclosed. In another aspect, a single-sided processing method for forming a nanopore device is disclosed to provide a device having baths on either side of a nanopore, which are addressable from a single side of the substrate. In yet another aspect, a method for fluidically addressing a plurality of nanopore devices is disclosed.Type: ApplicationFiled: July 20, 2018Publication date: March 28, 2019Inventors: Mangesh BANGAR, Joseph R. JOHNSON
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Patent number: 10234772Abstract: A calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.Type: GrantFiled: December 1, 2017Date of Patent: March 19, 2019Assignee: Applied Materials, Inc.Inventors: Mangesh Bangar, Bruce E. Adams, Kelly E. Hollar, Abhilash J. Mayur, Huixiong Dai, Jaujiun Chen
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Publication number: 20180136569Abstract: Embodiments disclosed herein relate to methods and systems for correcting overlay errors on a surface of a substrate. A processor performs a measurement process on a substrate to obtain an overlay error map. The processor determines an order of treatment for the substrate based on the overlay error map. The order of treatment includes one or more treatment processes. The processor generates a process recipe for a treatment process of the one or more treatment processes in the order of treatment. The processor provides the process recipe to a substrate treatment apparatus.Type: ApplicationFiled: November 13, 2017Publication date: May 17, 2018Inventors: Mangesh BANGAR, Srinivas D. NEMANI, Steve G. GHANAYEM, Ellie Y. YIEH
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Publication number: 20180101103Abstract: A calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.Type: ApplicationFiled: December 1, 2017Publication date: April 12, 2018Inventors: Mangesh BANGAR, Bruce E. ADAMS, Kelly E. HOLLAR, Abhilash J. MAYUR, Huixiong DAI, Jaujiun CHEN
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Patent number: 9864280Abstract: A calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.Type: GrantFiled: October 2, 2015Date of Patent: January 9, 2018Assignee: Applied Materials, Inc.Inventors: Mangesh Bangar, Bruce E. Adams, Kelly E. Hollar, Abhilash J Mayur, Huixiong Dai, Jaujiun Chen
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Publication number: 20170287752Abstract: Embodiments of the disclosure provide an integrated system for performing a measurement process and a lithographic overlay error correction process on a semiconductor substrate in a single processing system. In one embodiment, a processing system includes at least a load lock chamber, a transfer chamber coupled to the load lock chamber, an ion implantation processing chamber coupled to or in the transfer chamber, and a metrology tool coupled to the transfer chamber, wherein the metrology tool is adapted to obtain stress profile or an overlay error on a substrate disposed in the metrology tool.Type: ApplicationFiled: February 28, 2017Publication date: October 5, 2017Inventors: Ludovic GODET, Mehdi VAEZ-IRAVANI, Todd EGAN, Mangesh BANGAR, Concetta RICCOBENE, Abdul Aziz KHAJA, Srinivas D. NEMANI, Ellie Y. YIEH, Sean S. KANG
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Publication number: 20170097576Abstract: A calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.Type: ApplicationFiled: October 2, 2015Publication date: April 6, 2017Inventors: Mangesh Bangar, Bruce E. Adams, Kelly E. Hollar, Abhilash J. Mayur, Huixiong Dai, Jaujiun Chen
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Patent number: 9343309Abstract: Methods of laterally oxidizing features of a patterned substrate are described. A capping layer may be disposed above lateral features to laterally confine the oxidation. The oxidizable features may be material patterned near the optical resolution of a photolithography system using a high-resolution photomask. The oxidizable features may be wider than the spaces between the oxidizable features and may be about three times the width of the spaces. Oxidized portions may be formed on either side of repeated oxidizable features. The unoxidized portions may then be removed as part of a self-aligned double patterning (SADP) process. A gapfill layer deposited thereon may be etched or polished back to form alternating fill and non-sacrificial features.Type: GrantFiled: March 13, 2015Date of Patent: May 17, 2016Assignee: Applied Materials, Inc.Inventors: Mangesh Bangar, Liyan Miao, Huixiong Dai