Abstract: Deblocking filtering is provided in which an 8×8 filtering block covering eight sample vertical and horizontal boundary segments is divided into filtering sub-blocks that can be independently processed. To process the vertical boundary segment, the filtering block is divided into top and bottom 8×4 filtering sub-blocks, each covering a respective top and bottom half of the vertical boundary segment. To process the horizontal boundary segment, the filtering block is divided into left and right 4×8 filtering sub-blocks, each covering a respective left and right half of the horizontal boundary segment. The computation of the deviation d for a boundary segment in a filtering sub-block is performed using only samples from rows or columns in the filtering sub-block. Consequently, the filter on/off decisions and the weak/strong filtering decisions of the deblocking filtering are performed using samples contained within individual filtering blocks, thus allowing full parallel processing of the filtering blocks.

Abstract: Several methods and systems for encoding and decoding multimedia data are disclosed. In an embodiment, a system for decoding multimedia data includes a decoding module and an inverse transformation module. The inverse transformation module includes a first inverse transform module, a transpose buffer and a second inverse transform module. The decoding module decompresses encoded multimedia data using a pre-configurable scan order to provide a decompressed matrix of transform coefficients. The first inverse transform module inversely transforms the decompressed matrix of transform coefficients to provide an intermediate output matrix of transform coefficients, the transpose buffer transposes the intermediate output matrix to provide a transposed intermediate output matrix of transform coefficients, and the second inverse transform module inversely transforms the transposed intermediate output matrix of transform coefficients to provide inversely transformed multimedia data.

Abstract: Several systems, methods and integrated circuits capable of reducing blocking artifacts in video data are disclosed. In an embodiment, a system for reducing blocking artifacts in video data includes a processing module and a deblocking module. The deblocking module comprises a luma deblocking filter and a chroma deblocking filter configured to filter an edge between adjacent blocks associated with the video data, where a block of the adjacent blocks corresponds to one of a prediction block and a transform block. The processing module is communicatively associated with the deblocking module and is operable to configure at least one filter coefficient corresponding to the chroma deblocking filter based on one or more filter coefficients corresponding to the luma deblocking filter. The processing module is further configured to cause the chroma deblocking filter to filter the edge between the adjacent blocks based on the configured at least one filter coefficient.

Abstract: Several methods and systems for reducing blocking artifacts are disclosed. In an embodiment, the method includes receiving a pair of adjacent blocks having an edge being positioned between the adjacent blocks. The pair of adjacent blocks is associated with one or more coding blocks. The one or more coding blocks comprise one or more coding information associated with the coding of the pair of adjacent blocks. The method also includes conducting a determination of whether the pair of adjacent blocks is coded in a skip-mode based on the one or more coding information. The edge is filtered based on the determination. Filtering the edge comprises disabling a de-blocking filtering of the edge based on a determination that the pair of adjacent blocks is coded in the skip-mode; and enabling the de-blocking filtering of the edge based on determination that the pair of adjacent blocks is not associated with the skip-mode.

Abstract: A high-speed integer multiplier unit multiplying operands, wherein each operand can be either signed or unsigned. Type data is received for each operand which indicates whether the corresponding operand is to be treated as signed or unsigned. An extend bit is appended to each operand to provide extended operands, where the extend bit is the most significant bit of the corresponding operand if type data indicates that the operand is signed, and the extend bit is a logic zero otherwise. The extended operands are multiplied using a signed multiplication operation to provide the result. Overflow detection is done in parallel to the multiply operation, thus moving overflow-detection logic from the timing-critical path from the multiplier block's input to its output. The throughput performance of the multiplier unit is improved as a result.

Abstract: An architecture for a cascaded digital filters comprises independently programmable controlling registers and independent interpolating factors; a digital to analog converter for converting the digital signals into analog signals with a constant sampling rate which matches with the interpolating factors of the cascaded digital filters. Each filter property (filters order, coefficient symmetry, half-band, and poly-phase) can be programmed independently to support different system requirements and extract maximum throuput from a given hardware. The method of filtering digital signals comprises the steps of determining an interpolation factor of the cascaded digital filters with the lowest number of computations so as to match with the single sampling rate of the digital to analog converter, determining active filters and an interpolation factor of each digital filter in the cascaded digital filters, and determining a mode of operation of the cascaded digital filters.