Patents by Inventor Mangesh NIJASURE
Mangesh NIJASURE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10324805Abstract: Targeted chunking of data is described. A system identifies a length of a sliding window that a data chunking routine applies to a data buffer to create data chunks. The system identifies an expected chunk boundary in the data buffer. The system adjusts the expected chunk boundary, based on the length of the sliding window. The system enables the data chunking routine to start applying the sliding window at the adjusted expected chunk boundary in the data buffer instead of starting application of the sliding window at a beginning of the data buffer.Type: GrantFiled: October 3, 2016Date of Patent: June 18, 2019Assignee: EMC IP Holding Company LLCInventors: Kedar Patwardhan, Mangesh Nijasure
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Patent number: 9390554Abstract: Embodiments include an apparatus, a computer readable medium and a method for distributing tessellations within an accelerated processing device (APD) including at least two compute units. Embodiments include processing a plurality of patches in a first compute unit using a hull shader to generate hull shader output data. Once generated, hull shader output data is stored to an off-chip memory when tessellation factors associated with the shader program are greater than a configured threshold. Once stored in the off-chip memory, at least a portion of the hull shader output data is dynamically processed using a second compute unit.Type: GrantFiled: April 18, 2012Date of Patent: July 12, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Vineet Goel, Jason David Carroll, Mangesh Nijasure, Todd Martin
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Patent number: 9123153Abstract: Disclosed herein is a vertex core. The vertex core includes a reset scanner configured to remove reset indices and partial primitives in an input stream and resolve draw calls into sub-draw calls at reset index boundaries; and provide the resolved sub-draw calls to a plurality of downstream vertex grouper tessellators.Type: GrantFiled: May 22, 2012Date of Patent: September 1, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Jason Carroll, Vineet Goel, Mangesh Nijasure, Todd E. Martin
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Patent number: 9105125Abstract: A system, method and a computer-readable medium for load balancing patch processing pre-tessellation are provided. The patches for drawing objects on a display screen are distributed to shader engines for parallel processing. Each shader engine generates tessellation factors for a patch, wherein a value of generated tessellation factors for the patch is unknown prior to distribution. The patches are redistributed to the shader engines pre-tessellation to load balance the shader engines for processing the patches based on the value of tessellation factors in each patch.Type: GrantFiled: December 5, 2012Date of Patent: August 11, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Todd E. Martin, Mangesh Nijasure, Jason Carroll, Randy W. Ramsey, Brian A. Buchner
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Patent number: 8928679Abstract: A system, method and a computer program product are provided for distributing prim groups for parallel processing in a single clock cycle. A work distributor divides a draw call for primitive processing into a plurality of prim groups according to a prim group size. The work distributor then distributes the plurality of prim groups to a plurality of shader engines for parallel processing of the plurality of prim groups during a clock cycle. The size of a prim group and a number of prim groups are scaled to the plurality of shader engines.Type: GrantFiled: September 14, 2012Date of Patent: January 6, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Jason Carroll, Vineet Goel, Mangesh Nijasure, Todd E. Martin
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Patent number: 8884957Abstract: Disclosed herein methods, apparatuses, and systems for performing graphics processing. In this regard, a processing unit includes a tessellation module and a connectivity module. The tessellation module is configured to sequentially tessellate portions of a geometric shape to provide a series of tessellation points for the geometric shape. The connectivity module is configured to connect one or more groups of the tessellation points into one or more primitives in an order in which the series of tessellation points is provided.Type: GrantFiled: February 18, 2010Date of Patent: November 11, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Vineet Goel, Jason David Carroll, Brian Buchner, Mangesh Nijasure
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Patent number: 8854374Abstract: Methods, systems, and computer readable media embodiments are disclosed for generating primitives in a grid. Embodiments include generating a set of vertices in a section of the grid, selecting one or more vertices in the set of vertices in an order based on a proximity of the vertices to a boundary edge of the grid, and generating primitives based on the order of the selected vertices.Type: GrantFiled: December 23, 2011Date of Patent: October 7, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Todd Martin, Mangesh Nijasure, Vineet Goel, Jason David Carroll
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Publication number: 20140152675Abstract: A system, method and a computer-readable medium for load balancing patch processing pre-tessellation are provided. The patches for drawing objects on a display screen are distributed to shader engines for parallel processing. Each shader engine generates tessellation factors for a patch, wherein a value of generated tessellation factors for the patch is unknown prior to distribution. The patches are redistributed to the shader engines pre-tessellation to load balance the shader engines for processing the patches based on the value of tessellation factors in each patch.Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Applicant: Advanced Micro Devices, Inc.Inventors: Todd E. MARTIN, Mangesh Nijasure, Jason Carroll, Randy W. Ramsey, Brian A. Buchner
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Publication number: 20140078156Abstract: A system, method and a computer program product are provided for distributing prim groups for parallel processing in a single clock cycle. A work distributor divides a draw call for primitive processing into a plurality of prim groups according to a prim group size. The work distributor then distributes the plurality of prim groups to a plurality of shader engines for parallel processing of the plurality of prim groups during a clock cycle. The size of a prim group and a number of prim groups are scaled to the plurality of shader engines.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: Advanced Micro Devices, Inc.Inventors: Jason Carroll, Vineet Goel, Mangesh Nijasure, Todd E. Martin
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Publication number: 20130169634Abstract: Embodiments include an apparatus, a computer readable medium and a method for distributing tessellations within an accelerated processing device (APD) including at least two compute units. Embodiments include processing a plurality of patches in a first compute unit using a hull shader to generate hull shader output data. Once generated, hull shader output data is stored to an off-chip memory when tessellation factors associated with the shader program are greater than a configured threshold. Once stored in the off-chip memory, at least a portion of the hull shader output data is dynamically processed using a second compute unit.Type: ApplicationFiled: April 18, 2012Publication date: July 4, 2013Inventors: Vineet GOEL, Jason David Carroll, Mangesh Nijasure, Todd Martin
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Publication number: 20130169635Abstract: Disclosed herein is a vertex core. The vertex core includes a reset scanner configured to remove reset indices and partial primitives in an input stream and resolve draw calls into sub-draw calls at reset index boundaries; and provide the resolved sub-draw calls to a plurality of downstream vertex grouper tessellators.Type: ApplicationFiled: May 22, 2012Publication date: July 4, 2013Applicant: Advanced Micro Devices, Inc.Inventors: Jason CARROLL, Vineet GOEL, Mangesh NIJASURE, Todd E. MARTIN
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Publication number: 20130162651Abstract: Methods, systems, and computer readable media embodiments are disclosed for generating primitives in a grid. Embodiments include generating a set of vertices in a section of the grid, selecting one or more vertices in the set of vertices in an order based on a proximity of the vertices to a boundary edge of the grid, and generating primitives based on the order of the selected vertices.Type: ApplicationFiled: December 23, 2011Publication date: June 27, 2013Inventors: Todd Martin, Mangesh Nijasure, Vineet Goel, Jason David Carroll
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Publication number: 20120017062Abstract: Methods are disclosed for improving data processing performance in a processor using on-chip local memory in multiple processing units. According to an embodiment, a method of processing data elements in a processor using a plurality of processing units, includes: launching, in each of the processing units, a first wavefront having a first type of thread followed by a second wavefront having a second type of thread, where the first wavefront reads as input a portion of the data elements from an off-chip shared memory and generates a first output; writing the first output to an on-chip local memory of the respective processing unit; and writing to the on-chip local memory a second output generated by the second wavefront, where input to the second wavefront comprises a first plurality of data elements from the first output. Corresponding system and computer program product embodiments are also disclosed.Type: ApplicationFiled: July 19, 2011Publication date: January 19, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Vineet GOEL, Todd Martin, Mangesh Nijasure
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Publication number: 20110057931Abstract: Disclosed herein methods, apparatuses, and systems for performing graphics processing. In this regard, a processing unit includes a tessellation module and a connectivity module. The tessellation module is configured to sequentially tessellate portions of a geometric shape to provide a series of tessellation points for the geometric shape. The connectivity module is configured to connect one or more groups of the tessellation points into one or more primitives in an order in which the series of tessellation points is provided.Type: ApplicationFiled: February 18, 2010Publication date: March 10, 2011Inventors: Vineet GOEL, Jason David CARROLL, Brian BUCHNER, Mangesh NIJASURE